Layout reduction by sharing a column latch per two bit lines

Increasing levels of integration in successive generations of semiconductor memory products are possible through minimal metal-one layout pitches. An optimal bitline layout pitch in metal-one greatly exceeds an ability to match the pitch in a layout of a corresponding array of bitline-coupling-control latches. One latch controlling coupling for two bitlines alleviates the layout problem. In order for one latch to control coupling of two bitlines a logical segregation of the addressing of even and odd bitlines is necessary along with an additional odd or even bitline selection device in series with the selection device managed by the coupling control latch. With the use of a logical-to-physical address mapping and even-odd bitline selection, a single coupling control latch is able to manage one of two bitlines at a time. One latch serving two bitlines makes possible a bitline pitch attaining a maximum layout density possible for a fabrication process.