Ferroelectric polymer memory with a thick interface layer

Ferroelectric polymer memory with a thick interface layer

According to one aspect of the invention, a memory array and a method of constructing a memory array are provided. An insulating layer is formed on a semiconductor substrate. A first metal stack is then formed on the insulating layer. The first metal stack is etched to form first metal lines. A poly...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Richards, Mark R, Diana, Daniel C, Windlass, Hitesh, Ford, Wayne K, Andideh, Ebrahim
Format: Patent
Sprache:eng
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator Richards, Mark R
Diana, Daniel C
Windlass, Hitesh
Ford, Wayne K
Andideh, Ebrahim
description According to one aspect of the invention, a memory array and a method of constructing a memory array are provided. An insulating layer is formed on a semiconductor substrate. A first metal stack is then formed on the insulating layer. The first metal stack is etched to form first metal lines. A polymeric layer is formed over the first metal lines and the insulating layer. The polymeric layer has a surface with a plurality of roughness formations. A second metal stack is formed on the polymeric layer with an interface layer, which is thicker than the heights of the roughness formations. Then the second metal stack is etched to form second metal lines. Memory cells are formed wherever a second metal line extends over a first metal line.
format Patent
fullrecord <record><control><sourceid>uspatents_EFH</sourceid><recordid>TN_cdi_uspatents_grants_07223613</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>07223613</sourcerecordid><originalsourceid>FETCH-uspatents_grants_072236133</originalsourceid><addsrcrecordid>eNrjZLB0Sy0qyk_NSU0uKcpMVijIz6nMTS1SyE3NzS-qVCjPLMlQSFQoychMzlbIzCtJLUpLTE5VyEmsTC3iYWBNS8wpTuWF0twMCm6uIc4euqXFBYklqXklxfHpRYkgysDcyMjYzNDYmAglADPJL8Y</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Ferroelectric polymer memory with a thick interface layer</title><source>USPTO Issued Patents</source><creator>Richards, Mark R ; Diana, Daniel C ; Windlass, Hitesh ; Ford, Wayne K ; Andideh, Ebrahim</creator><creatorcontrib>Richards, Mark R ; Diana, Daniel C ; Windlass, Hitesh ; Ford, Wayne K ; Andideh, Ebrahim ; Intel Corporation</creatorcontrib><description>According to one aspect of the invention, a memory array and a method of constructing a memory array are provided. An insulating layer is formed on a semiconductor substrate. A first metal stack is then formed on the insulating layer. The first metal stack is etched to form first metal lines. A polymeric layer is formed over the first metal lines and the insulating layer. The polymeric layer has a surface with a plurality of roughness formations. A second metal stack is formed on the polymeric layer with an interface layer, which is thicker than the heights of the roughness formations. Then the second metal stack is etched to form second metal lines. Memory cells are formed wherever a second metal line extends over a first metal line.</description><language>eng</language><creationdate>2007</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7223613$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,780,802,885,64039</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7223613$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Richards, Mark R</creatorcontrib><creatorcontrib>Diana, Daniel C</creatorcontrib><creatorcontrib>Windlass, Hitesh</creatorcontrib><creatorcontrib>Ford, Wayne K</creatorcontrib><creatorcontrib>Andideh, Ebrahim</creatorcontrib><creatorcontrib>Intel Corporation</creatorcontrib><title>Ferroelectric polymer memory with a thick interface layer</title><description>According to one aspect of the invention, a memory array and a method of constructing a memory array are provided. An insulating layer is formed on a semiconductor substrate. A first metal stack is then formed on the insulating layer. The first metal stack is etched to form first metal lines. A polymeric layer is formed over the first metal lines and the insulating layer. The polymeric layer has a surface with a plurality of roughness formations. A second metal stack is formed on the polymeric layer with an interface layer, which is thicker than the heights of the roughness formations. Then the second metal stack is etched to form second metal lines. Memory cells are formed wherever a second metal line extends over a first metal line.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2007</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNrjZLB0Sy0qyk_NSU0uKcpMVijIz6nMTS1SyE3NzS-qVCjPLMlQSFQoychMzlbIzCtJLUpLTE5VyEmsTC3iYWBNS8wpTuWF0twMCm6uIc4euqXFBYklqXklxfHpRYkgysDcyMjYzNDYmAglADPJL8Y</recordid><startdate>20070529</startdate><enddate>20070529</enddate><creator>Richards, Mark R</creator><creator>Diana, Daniel C</creator><creator>Windlass, Hitesh</creator><creator>Ford, Wayne K</creator><creator>Andideh, Ebrahim</creator><scope>EFH</scope></search><sort><creationdate>20070529</creationdate><title>Ferroelectric polymer memory with a thick interface layer</title><author>Richards, Mark R ; Diana, Daniel C ; Windlass, Hitesh ; Ford, Wayne K ; Andideh, Ebrahim</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_072236133</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2007</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Richards, Mark R</creatorcontrib><creatorcontrib>Diana, Daniel C</creatorcontrib><creatorcontrib>Windlass, Hitesh</creatorcontrib><creatorcontrib>Ford, Wayne K</creatorcontrib><creatorcontrib>Andideh, Ebrahim</creatorcontrib><creatorcontrib>Intel Corporation</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Richards, Mark R</au><au>Diana, Daniel C</au><au>Windlass, Hitesh</au><au>Ford, Wayne K</au><au>Andideh, Ebrahim</au><aucorp>Intel Corporation</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Ferroelectric polymer memory with a thick interface layer</title><date>2007-05-29</date><risdate>2007</risdate><abstract>According to one aspect of the invention, a memory array and a method of constructing a memory array are provided. An insulating layer is formed on a semiconductor substrate. A first metal stack is then formed on the insulating layer. The first metal stack is etched to form first metal lines. A polymeric layer is formed over the first metal lines and the insulating layer. The polymeric layer has a surface with a plurality of roughness formations. A second metal stack is formed on the polymeric layer with an interface layer, which is thicker than the heights of the roughness formations. Then the second metal stack is etched to form second metal lines. Memory cells are formed wherever a second metal line extends over a first metal line.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_uspatents_grants_07223613
source USPTO Issued Patents
title Ferroelectric polymer memory with a thick interface layer
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-02T21%3A03%3A50IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-uspatents_EFH&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Richards,%20Mark%20R&rft.aucorp=Intel%20Corporation&rft.date=2007-05-29&rft_id=info:doi/&rft_dat=%3Cuspatents_EFH%3E07223613%3C/uspatents_EFH%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true