Ground bounce protection circuit for a test mode pin
A test-mode circuit allows the same pad of a semiconductor device to be used as a test pad during test operations and as an I/O pad during normal operations. The test-mode circuit is coupled between the pad and a reference signal (Vbg) of the device, and in response to a control signal (CTRL) either...
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Patent |
| Sprache: | eng |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | Zhou, Shi-dong Huang, Gubo |
| description | A test-mode circuit allows the same pad of a semiconductor device to be used as a test pad during test operations and as an I/O pad during normal operations. The test-mode circuit is coupled between the pad and a reference signal (Vbg) of the device, and in response to a control signal (CTRL) either couples the pad and the reference signal (Vbg) together or isolates the pad and the reference signal (Vbg) from each other. The test-mode circuit includes at least one NMOS transistor (MN) and a PMOS transistor (MP) connected in series between the pad and the reference signal (Vbg). During normal operation, the NMOS transistor (MN) isolates the reference signal (Vbg) from the pad, and the PMOS transistor (MP) compensates for voltage undershoot conditions at the pad. |
| format | Patent |
| fullrecord | <record><control><sourceid>uspatents_EFH</sourceid><recordid>TN_cdi_uspatents_grants_07212060</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>07212060</sourcerecordid><originalsourceid>FETCH-uspatents_grants_072120603</originalsourceid><addsrcrecordid>eNrjZDBxL8ovzUtRSAKSyakKBUX5JanJJZn5eQrJmUXJpZklCmn5RQqJCiWpxSUKufkpQCWZeTwMrGmJOcWpvFCam0HBzTXE2UO3tLggsSQ1r6Q4Pr0oEUQZmBsZGhmYGRgToQQA9f4tZg</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Ground bounce protection circuit for a test mode pin</title><source>USPTO Issued Patents</source><creator>Zhou, Shi-dong ; Huang, Gubo</creator><creatorcontrib>Zhou, Shi-dong ; Huang, Gubo ; Xilinx, Inc</creatorcontrib><description>A test-mode circuit allows the same pad of a semiconductor device to be used as a test pad during test operations and as an I/O pad during normal operations. The test-mode circuit is coupled between the pad and a reference signal (Vbg) of the device, and in response to a control signal (CTRL) either couples the pad and the reference signal (Vbg) together or isolates the pad and the reference signal (Vbg) from each other. The test-mode circuit includes at least one NMOS transistor (MN) and a PMOS transistor (MP) connected in series between the pad and the reference signal (Vbg). During normal operation, the NMOS transistor (MN) isolates the reference signal (Vbg) from the pad, and the PMOS transistor (MP) compensates for voltage undershoot conditions at the pad.</description><language>eng</language><creationdate>2007</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7212060$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,780,802,885,64038</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7212060$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Zhou, Shi-dong</creatorcontrib><creatorcontrib>Huang, Gubo</creatorcontrib><creatorcontrib>Xilinx, Inc</creatorcontrib><title>Ground bounce protection circuit for a test mode pin</title><description>A test-mode circuit allows the same pad of a semiconductor device to be used as a test pad during test operations and as an I/O pad during normal operations. The test-mode circuit is coupled between the pad and a reference signal (Vbg) of the device, and in response to a control signal (CTRL) either couples the pad and the reference signal (Vbg) together or isolates the pad and the reference signal (Vbg) from each other. The test-mode circuit includes at least one NMOS transistor (MN) and a PMOS transistor (MP) connected in series between the pad and the reference signal (Vbg). During normal operation, the NMOS transistor (MN) isolates the reference signal (Vbg) from the pad, and the PMOS transistor (MP) compensates for voltage undershoot conditions at the pad.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2007</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNrjZDBxL8ovzUtRSAKSyakKBUX5JanJJZn5eQrJmUXJpZklCmn5RQqJCiWpxSUKufkpQCWZeTwMrGmJOcWpvFCam0HBzTXE2UO3tLggsSQ1r6Q4Pr0oEUQZmBsZGhmYGRgToQQA9f4tZg</recordid><startdate>20070501</startdate><enddate>20070501</enddate><creator>Zhou, Shi-dong</creator><creator>Huang, Gubo</creator><scope>EFH</scope></search><sort><creationdate>20070501</creationdate><title>Ground bounce protection circuit for a test mode pin</title><author>Zhou, Shi-dong ; Huang, Gubo</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_072120603</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2007</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Zhou, Shi-dong</creatorcontrib><creatorcontrib>Huang, Gubo</creatorcontrib><creatorcontrib>Xilinx, Inc</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Zhou, Shi-dong</au><au>Huang, Gubo</au><aucorp>Xilinx, Inc</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Ground bounce protection circuit for a test mode pin</title><date>2007-05-01</date><risdate>2007</risdate><abstract>A test-mode circuit allows the same pad of a semiconductor device to be used as a test pad during test operations and as an I/O pad during normal operations. The test-mode circuit is coupled between the pad and a reference signal (Vbg) of the device, and in response to a control signal (CTRL) either couples the pad and the reference signal (Vbg) together or isolates the pad and the reference signal (Vbg) from each other. The test-mode circuit includes at least one NMOS transistor (MN) and a PMOS transistor (MP) connected in series between the pad and the reference signal (Vbg). During normal operation, the NMOS transistor (MN) isolates the reference signal (Vbg) from the pad, and the PMOS transistor (MP) compensates for voltage undershoot conditions at the pad.</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng |
| recordid | cdi_uspatents_grants_07212060 |
| source | USPTO Issued Patents |
| title | Ground bounce protection circuit for a test mode pin |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-13T00%3A47%3A47IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-uspatents_EFH&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Zhou,%20Shi-dong&rft.aucorp=Xilinx,%20Inc&rft.date=2007-05-01&rft_id=info:doi/&rft_dat=%3Cuspatents_EFH%3E07212060%3C/uspatents_EFH%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |