Semiconductor integrated circuit and method of designing the same
According to the present invention, a semiconductor integrated circuit having a cell region in which a plurality of MOS transistors forming at least one cell are placed; and first and second power lines placed along one direction in a peripheral portion of the cell region, wherein in the cell region...
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creator | Kobayashi, Tsuguo |
description | According to the present invention, a semiconductor integrated circuit having a cell region in which a plurality of MOS transistors forming at least one cell are placed; and first and second power lines placed along one direction in a peripheral portion of the cell region, wherein in the cell region, gate grids for defining a first pitch in the one direction and pin grids for defining a second pitch in the one direction are set, gate electrodes of the MOS transistors are placed in accordance with the gate grids, and an interconnection layer is placed in accordance with the pin grids. |
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fullrecord | <record><control><sourceid>uspatents_EFH</sourceid><recordid>TN_cdi_uspatents_grants_07205191</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>07205191</sourcerecordid><originalsourceid>FETCH-uspatents_grants_072051913</originalsourceid><addsrcrecordid>eNrjZHAMTs3NTM7PSylNLskvUsjMK0lNL0osSU1RSM4sSi7NLFFIzEtRyE0tychPUchPU0hJLc5Mz8vMS1coyUhVKE7MTeVhYE1LzClO5YXS3AwKbq4hzh66pcUFQIPySorjgSaCKANzIwNTQ0tDYyKUAADtKDKp</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Semiconductor integrated circuit and method of designing the same</title><source>USPTO Issued Patents</source><creator>Kobayashi, Tsuguo</creator><creatorcontrib>Kobayashi, Tsuguo ; Kabushiki Kaisha Toshiba</creatorcontrib><description>According to the present invention, a semiconductor integrated circuit having a cell region in which a plurality of MOS transistors forming at least one cell are placed; and first and second power lines placed along one direction in a peripheral portion of the cell region, wherein in the cell region, gate grids for defining a first pitch in the one direction and pin grids for defining a second pitch in the one direction are set, gate electrodes of the MOS transistors are placed in accordance with the gate grids, and an interconnection layer is placed in accordance with the pin grids.</description><language>eng</language><creationdate>2007</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7205191$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,777,799,882,64018</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7205191$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Kobayashi, Tsuguo</creatorcontrib><creatorcontrib>Kabushiki Kaisha Toshiba</creatorcontrib><title>Semiconductor integrated circuit and method of designing the same</title><description>According to the present invention, a semiconductor integrated circuit having a cell region in which a plurality of MOS transistors forming at least one cell are placed; and first and second power lines placed along one direction in a peripheral portion of the cell region, wherein in the cell region, gate grids for defining a first pitch in the one direction and pin grids for defining a second pitch in the one direction are set, gate electrodes of the MOS transistors are placed in accordance with the gate grids, and an interconnection layer is placed in accordance with the pin grids.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2007</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNrjZHAMTs3NTM7PSylNLskvUsjMK0lNL0osSU1RSM4sSi7NLFFIzEtRyE0tychPUchPU0hJLc5Mz8vMS1coyUhVKE7MTeVhYE1LzClO5YXS3AwKbq4hzh66pcUFQIPySorjgSaCKANzIwNTQ0tDYyKUAADtKDKp</recordid><startdate>20070417</startdate><enddate>20070417</enddate><creator>Kobayashi, Tsuguo</creator><scope>EFH</scope></search><sort><creationdate>20070417</creationdate><title>Semiconductor integrated circuit and method of designing the same</title><author>Kobayashi, Tsuguo</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_072051913</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2007</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Kobayashi, Tsuguo</creatorcontrib><creatorcontrib>Kabushiki Kaisha Toshiba</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Kobayashi, Tsuguo</au><aucorp>Kabushiki Kaisha Toshiba</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Semiconductor integrated circuit and method of designing the same</title><date>2007-04-17</date><risdate>2007</risdate><abstract>According to the present invention, a semiconductor integrated circuit having a cell region in which a plurality of MOS transistors forming at least one cell are placed; and first and second power lines placed along one direction in a peripheral portion of the cell region, wherein in the cell region, gate grids for defining a first pitch in the one direction and pin grids for defining a second pitch in the one direction are set, gate electrodes of the MOS transistors are placed in accordance with the gate grids, and an interconnection layer is placed in accordance with the pin grids.</abstract><oa>free_for_read</oa></addata></record> |
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title | Semiconductor integrated circuit and method of designing the same |
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