Designing scan chains with specific parameter sensitivities to identify process defects

A method is disclosed for designing scan chains in an integrated circuit chip with specific parameter sensitivities to identify fabrication process defects causing test fails and chip yield loss. The composition of scan paths in the integrated circuit chip is biased to allow them to also function as...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Adkisson, James W, Bazan, Greg, Cohn, John M, Grady, Matthew S, Huisman, Leendert M, Jaffe, Mark D, Nigh, Phillip J, Pastel, Leah M. P, Sopchak, Thomas G, Sweenor, David E, Vallett, David P
Format:	Patent
Sprache:	eng
Online-Zugang:	Volltext bestellen
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