Method and circuit arrangement for memory error processing

Method and circuit arrangement for memory error processing

The present invention relates to a method and circuit arrangement for performing an error correction in a memory arrangement in which a redundancy system is used. The addresses of faulty cells are recorded redundantly by applying a corresponding coding. Then, an error correction is applied to the fa...

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Hauptverfasser: Ditewig, Anthonie Meindert Herman, Cuppens, Roger, Salters, Roelof Herman Willem
Format: Patent
Sprache:eng
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creator Ditewig, Anthonie Meindert Herman
Cuppens, Roger
Salters, Roelof Herman Willem
description The present invention relates to a method and circuit arrangement for performing an error correction in a memory arrangement in which a redundancy system is used. The addresses of faulty cells are recorded redundantly by applying a corresponding coding. Then, an error correction is applied to the faulty-address information before it is compared to an externally applied address. Thereby, errors due to faulty redundancy addresses can be prevented.
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title Method and circuit arrangement for memory error processing
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