Systems and methods for minimizing harmonic interference
Systems and methods are disclosed for minimizing nth-order harmonic associated with a square wave clock signal having a predetermined frequency and duty cycle. The system changes the duty cycle of the clock to eliminate or suppress the nth-order harmonic of the clock; and generates a low-interferenc...
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| creator | Azmoodeh, Masoud |
| description | Systems and methods are disclosed for minimizing nth-order harmonic associated with a square wave clock signal having a predetermined frequency and duty cycle. The system changes the duty cycle of the clock to eliminate or suppress the nth-order harmonic of the clock; and generates a low-interference clock having the changed duty cycle while keeping the predetermined frequency. |
| format | Patent |
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| language | eng |
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| source | USPTO Issued Patents |
| title | Systems and methods for minimizing harmonic interference |
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