Method and apparatus to establish safe state in a volatile computer memory under multiple hardware and software malfunction conditions

Volatile memory is placed into a data-preserving safe state in a computer system in response to any one of a reduction in power applied to the volatile memory, a bus reset signal on a data communication bus of the computer system, and an absence of a bus clock signal on the bus. The volatile memory...

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Hauptverfasser: Kilbourne, Allen, Reger, Brad A, Valin, Steve
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creator Kilbourne, Allen
Reger, Brad A
Valin, Steve
description Volatile memory is placed into a data-preserving safe state in a computer system in response to any one of a reduction in power applied to the volatile memory, a bus reset signal on a data communication bus of the computer system, and an absence of a bus clock signal on the bus. The volatile memory is powered from an auxiliary uninterruptible power supply in response to the reduction in power. The volatile memory is also placed into the data-preserving safe state in response to a cessation in executing software instructions by a CPU of the computer system. Placing the volatile memory into the safe state in response to and under these conditions enhances the opportunity to preserve data in response to error and malfunction conditions.
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fullrecord <record><control><sourceid>uspatents_EFH</sourceid><recordid>TN_cdi_uspatents_grants_07139937</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>07139937</sourcerecordid><originalsourceid>FETCH-uspatents_grants_071399373</originalsourceid><addsrcrecordid>eNqNjTEOwjAMRbswIOAOvgASqEPVGYFY2NiRaRwaKXGi2AFxAc5NWnEAhq__n2z9v2w-F9IxGkCuSgkzahHQCCSKd-9kBEFLUEkJHAPCM3pU5wmGGFJRyhAoxPyGwmaC4tWleh4xmxdmmrslWp0hoLeFB3WRawEbNyVZNwuLXmjz81UDp-P1cN4WSXWYVW6PjJPtun3b923X_vHyBRrXTWA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method and apparatus to establish safe state in a volatile computer memory under multiple hardware and software malfunction conditions</title><source>USPTO Issued Patents</source><creator>Kilbourne, Allen ; Reger, Brad A ; Valin, Steve</creator><creatorcontrib>Kilbourne, Allen ; Reger, Brad A ; Valin, Steve ; Network Appliance, Inc</creatorcontrib><description>Volatile memory is placed into a data-preserving safe state in a computer system in response to any one of a reduction in power applied to the volatile memory, a bus reset signal on a data communication bus of the computer system, and an absence of a bus clock signal on the bus. The volatile memory is powered from an auxiliary uninterruptible power supply in response to the reduction in power. The volatile memory is also placed into the data-preserving safe state in response to a cessation in executing software instructions by a CPU of the computer system. Placing the volatile memory into the safe state in response to and under these conditions enhances the opportunity to preserve data in response to error and malfunction conditions.</description><language>eng</language><creationdate>2006</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7139937$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,776,798,881,64012</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7139937$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Kilbourne, Allen</creatorcontrib><creatorcontrib>Reger, Brad A</creatorcontrib><creatorcontrib>Valin, Steve</creatorcontrib><creatorcontrib>Network Appliance, Inc</creatorcontrib><title>Method and apparatus to establish safe state in a volatile computer memory under multiple hardware and software malfunction conditions</title><description>Volatile memory is placed into a data-preserving safe state in a computer system in response to any one of a reduction in power applied to the volatile memory, a bus reset signal on a data communication bus of the computer system, and an absence of a bus clock signal on the bus. The volatile memory is powered from an auxiliary uninterruptible power supply in response to the reduction in power. The volatile memory is also placed into the data-preserving safe state in response to a cessation in executing software instructions by a CPU of the computer system. Placing the volatile memory into the safe state in response to and under these conditions enhances the opportunity to preserve data in response to error and malfunction conditions.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2006</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNqNjTEOwjAMRbswIOAOvgASqEPVGYFY2NiRaRwaKXGi2AFxAc5NWnEAhq__n2z9v2w-F9IxGkCuSgkzahHQCCSKd-9kBEFLUEkJHAPCM3pU5wmGGFJRyhAoxPyGwmaC4tWleh4xmxdmmrslWp0hoLeFB3WRawEbNyVZNwuLXmjz81UDp-P1cN4WSXWYVW6PjJPtun3b923X_vHyBRrXTWA</recordid><startdate>20061121</startdate><enddate>20061121</enddate><creator>Kilbourne, Allen</creator><creator>Reger, Brad A</creator><creator>Valin, Steve</creator><scope>EFH</scope></search><sort><creationdate>20061121</creationdate><title>Method and apparatus to establish safe state in a volatile computer memory under multiple hardware and software malfunction conditions</title><author>Kilbourne, Allen ; Reger, Brad A ; Valin, Steve</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_071399373</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2006</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Kilbourne, Allen</creatorcontrib><creatorcontrib>Reger, Brad A</creatorcontrib><creatorcontrib>Valin, Steve</creatorcontrib><creatorcontrib>Network Appliance, Inc</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Kilbourne, Allen</au><au>Reger, Brad A</au><au>Valin, Steve</au><aucorp>Network Appliance, Inc</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method and apparatus to establish safe state in a volatile computer memory under multiple hardware and software malfunction conditions</title><date>2006-11-21</date><risdate>2006</risdate><abstract>Volatile memory is placed into a data-preserving safe state in a computer system in response to any one of a reduction in power applied to the volatile memory, a bus reset signal on a data communication bus of the computer system, and an absence of a bus clock signal on the bus. The volatile memory is powered from an auxiliary uninterruptible power supply in response to the reduction in power. The volatile memory is also placed into the data-preserving safe state in response to a cessation in executing software instructions by a CPU of the computer system. Placing the volatile memory into the safe state in response to and under these conditions enhances the opportunity to preserve data in response to error and malfunction conditions.</abstract><oa>free_for_read</oa></addata></record>
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title Method and apparatus to establish safe state in a volatile computer memory under multiple hardware and software malfunction conditions
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-04T16%3A43%3A42IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-uspatents_EFH&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Kilbourne,%20Allen&rft.aucorp=Network%20Appliance,%20Inc&rft.date=2006-11-21&rft_id=info:doi/&rft_dat=%3Cuspatents_EFH%3E07139937%3C/uspatents_EFH%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true