Method of making transistor with strained source/drain

Method of making transistor with strained source/drain

A method of fabricating a transistor comprises the steps of: forming a gate electrode above a substrate made of a first semiconductor material having a first lattice spacing, forming recesses in the semiconductor substrate at respective locations where a source region and a drain region are to be fo...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Chen, Yun-Hsiu, Jang, Syun-Ming
Format: Patent
Sprache:eng
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator Chen, Yun-Hsiu
Jang, Syun-Ming
description A method of fabricating a transistor comprises the steps of: forming a gate electrode above a substrate made of a first semiconductor material having a first lattice spacing, forming recesses in the semiconductor substrate at respective locations where a source region and a drain region are to be formed, epitaxially growing a second semiconductor material having a second lattice spacing different from the first lattice spacing in the recesses, and implanting a dopant in the second semiconductor material after the growing step.
format Patent
fullrecord <record><control><sourceid>uspatents_EFH</sourceid><recordid>TN_cdi_uspatents_grants_07118952</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>07118952</sourcerecordid><originalsourceid>FETCH-uspatents_grants_071189523</originalsourceid><addsrcrecordid>eNrjZDDzTS3JyE9RyE9TyE3MzsxLVygpSswrziwuyS9SKM8syVAoBgpk5qWmKBTnlxYlp-qngLg8DKxpiTnFqbxQmptBwc01xNlDt7S4ILEkNa-kOD4daA6QMjA3NLSwNDUyJkIJAIarLrc</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method of making transistor with strained source/drain</title><source>USPTO Issued Patents</source><creator>Chen, Yun-Hsiu ; Jang, Syun-Ming</creator><creatorcontrib>Chen, Yun-Hsiu ; Jang, Syun-Ming ; Taiwan Semiconductor Manufacturing Co., Ltd</creatorcontrib><description>A method of fabricating a transistor comprises the steps of: forming a gate electrode above a substrate made of a first semiconductor material having a first lattice spacing, forming recesses in the semiconductor substrate at respective locations where a source region and a drain region are to be formed, epitaxially growing a second semiconductor material having a second lattice spacing different from the first lattice spacing in the recesses, and implanting a dopant in the second semiconductor material after the growing step.</description><language>eng</language><creationdate>2006</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7118952$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,780,802,885,64039</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7118952$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Chen, Yun-Hsiu</creatorcontrib><creatorcontrib>Jang, Syun-Ming</creatorcontrib><creatorcontrib>Taiwan Semiconductor Manufacturing Co., Ltd</creatorcontrib><title>Method of making transistor with strained source/drain</title><description>A method of fabricating a transistor comprises the steps of: forming a gate electrode above a substrate made of a first semiconductor material having a first lattice spacing, forming recesses in the semiconductor substrate at respective locations where a source region and a drain region are to be formed, epitaxially growing a second semiconductor material having a second lattice spacing different from the first lattice spacing in the recesses, and implanting a dopant in the second semiconductor material after the growing step.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2006</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNrjZDDzTS3JyE9RyE9TyE3MzsxLVygpSswrziwuyS9SKM8syVAoBgpk5qWmKBTnlxYlp-qngLg8DKxpiTnFqbxQmptBwc01xNlDt7S4ILEkNa-kOD4daA6QMjA3NLSwNDUyJkIJAIarLrc</recordid><startdate>20061010</startdate><enddate>20061010</enddate><creator>Chen, Yun-Hsiu</creator><creator>Jang, Syun-Ming</creator><scope>EFH</scope></search><sort><creationdate>20061010</creationdate><title>Method of making transistor with strained source/drain</title><author>Chen, Yun-Hsiu ; Jang, Syun-Ming</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_071189523</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2006</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Chen, Yun-Hsiu</creatorcontrib><creatorcontrib>Jang, Syun-Ming</creatorcontrib><creatorcontrib>Taiwan Semiconductor Manufacturing Co., Ltd</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Chen, Yun-Hsiu</au><au>Jang, Syun-Ming</au><aucorp>Taiwan Semiconductor Manufacturing Co., Ltd</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method of making transistor with strained source/drain</title><date>2006-10-10</date><risdate>2006</risdate><abstract>A method of fabricating a transistor comprises the steps of: forming a gate electrode above a substrate made of a first semiconductor material having a first lattice spacing, forming recesses in the semiconductor substrate at respective locations where a source region and a drain region are to be formed, epitaxially growing a second semiconductor material having a second lattice spacing different from the first lattice spacing in the recesses, and implanting a dopant in the second semiconductor material after the growing step.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_uspatents_grants_07118952
source USPTO Issued Patents
title Method of making transistor with strained source/drain
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-25T07%3A24%3A05IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-uspatents_EFH&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Chen,%20Yun-Hsiu&rft.aucorp=Taiwan%20Semiconductor%20Manufacturing%20Co.,%20Ltd&rft.date=2006-10-10&rft_id=info:doi/&rft_dat=%3Cuspatents_EFH%3E07118952%3C/uspatents_EFH%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true