Interlaced delay-locked loops for controlling memory-circuit timing

For control, some memory circuits use a delay-locked loop to generate a set of signals, each delayed a different amount relative a reference signal. However, as circuits get faster and faster, conventional delay-locked loops require use of extra interpolation circuitry to generate smaller delays, an...

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Bibliographische Detailangaben

1. Verfasser:	Harrison, Ronnie M
Format:	Patent
Sprache:	eng
Online-Zugang:	Volltext bestellen
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