Method of reducing the number of configuration bits by eliminating the unused configuration bits

Method of reducing the number of configuration bits by eliminating the unused configuration bits

Apparatus and method configures a programmable logic device (PLD). The method includes reading a first configuration frame from the PLD. The first configuration frame indicates used and unused bit positions. The method further includes reading a second configuration frame from a memory. The second c...

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1. Verfasser: Do, Toan D
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creator Do, Toan D
description Apparatus and method configures a programmable logic device (PLD). The method includes reading a first configuration frame from the PLD. The first configuration frame indicates used and unused bit positions. The method further includes reading a second configuration frame from a memory. The second configuration frame is related to the first configuration frame. The method further includes creating a third configuration frame by placing information from the second configuration frame into positions indicated by the first configuration frame. The method further includes configuring the PLD using the third configuration frame. In this manner, the second configuration frame may occupy less space in the memory, and may be read more quickly, than a frame that also included position information.
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fullrecord <record><control><sourceid>uspatents_EFH</sourceid><recordid>TN_cdi_uspatents_grants_06985011</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>06985011</sourcerecordid><originalsourceid>FETCH-uspatents_grants_069850113</originalsourceid><addsrcrecordid>eNrjZEjwTS3JyE9RyE9TKEpNKU3OzEtXKMlIVcgrzU1KLQIJJ-fnpWWmlxYllmTm5ykkZZYUKyRVKqTmZOZm5gHFoOpL80qLU1OwKOZhYE1LzClO5YXS3AwKbq4hzh66pcUFiSWpeSXF8elFiSDKwMzSwtTA0NCYCCUAjfg-jA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method of reducing the number of configuration bits by eliminating the unused configuration bits</title><source>USPTO Issued Patents</source><creator>Do, Toan D</creator><creatorcontrib>Do, Toan D ; Altera Corporation</creatorcontrib><description>Apparatus and method configures a programmable logic device (PLD). The method includes reading a first configuration frame from the PLD. The first configuration frame indicates used and unused bit positions. The method further includes reading a second configuration frame from a memory. The second configuration frame is related to the first configuration frame. The method further includes creating a third configuration frame by placing information from the second configuration frame into positions indicated by the first configuration frame. The method further includes configuring the PLD using the third configuration frame. In this manner, the second configuration frame may occupy less space in the memory, and may be read more quickly, than a frame that also included position information.</description><language>eng</language><creationdate>2006</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6985011$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,780,802,885,64028</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6985011$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Do, Toan D</creatorcontrib><creatorcontrib>Altera Corporation</creatorcontrib><title>Method of reducing the number of configuration bits by eliminating the unused configuration bits</title><description>Apparatus and method configures a programmable logic device (PLD). The method includes reading a first configuration frame from the PLD. The first configuration frame indicates used and unused bit positions. The method further includes reading a second configuration frame from a memory. The second configuration frame is related to the first configuration frame. The method further includes creating a third configuration frame by placing information from the second configuration frame into positions indicated by the first configuration frame. The method further includes configuring the PLD using the third configuration frame. In this manner, the second configuration frame may occupy less space in the memory, and may be read more quickly, than a frame that also included position information.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2006</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNrjZEjwTS3JyE9RyE9TKEpNKU3OzEtXKMlIVcgrzU1KLQIJJ-fnpWWmlxYllmTm5ykkZZYUKyRVKqTmZOZm5gHFoOpL80qLU1OwKOZhYE1LzClO5YXS3AwKbq4hzh66pcUFiSWpeSXF8elFiSDKwMzSwtTA0NCYCCUAjfg-jA</recordid><startdate>20060110</startdate><enddate>20060110</enddate><creator>Do, Toan D</creator><scope>EFH</scope></search><sort><creationdate>20060110</creationdate><title>Method of reducing the number of configuration bits by eliminating the unused configuration bits</title><author>Do, Toan D</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_069850113</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2006</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Do, Toan D</creatorcontrib><creatorcontrib>Altera Corporation</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Do, Toan D</au><aucorp>Altera Corporation</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method of reducing the number of configuration bits by eliminating the unused configuration bits</title><date>2006-01-10</date><risdate>2006</risdate><abstract>Apparatus and method configures a programmable logic device (PLD). The method includes reading a first configuration frame from the PLD. The first configuration frame indicates used and unused bit positions. The method further includes reading a second configuration frame from a memory. The second configuration frame is related to the first configuration frame. The method further includes creating a third configuration frame by placing information from the second configuration frame into positions indicated by the first configuration frame. The method further includes configuring the PLD using the third configuration frame. In this manner, the second configuration frame may occupy less space in the memory, and may be read more quickly, than a frame that also included position information.</abstract><oa>free_for_read</oa></addata></record>
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title Method of reducing the number of configuration bits by eliminating the unused configuration bits
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-14T18%3A44%3A58IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-uspatents_EFH&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Do,%20Toan%20D&rft.aucorp=Altera%20Corporation&rft.date=2006-01-10&rft_id=info:doi/&rft_dat=%3Cuspatents_EFH%3E06985011%3C/uspatents_EFH%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true