Error insertion circuit for SONET forward error correction

An OC-192 front-end application-specific integrated circuit (ASIC) de-interleaves an OC-192 signal to create four OC-48 signals, and decodes error-correction codes embedded in each of the four OC-48 signals. An error insertion circuit is also provided for verifying correct operation of encoding and...

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Hauptverfasser: Duschatko, Douglas E, Thurston, Andrew J
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Thurston, Andrew J
description An OC-192 front-end application-specific integrated circuit (ASIC) de-interleaves an OC-192 signal to create four OC-48 signals, and decodes error-correction codes embedded in each of the four OC-48 signals. An error insertion circuit is also provided for verifying correct operation of encoding and decoding circuits. A desired number of errors may be programmed for insertion into the OC-48 data signals. Error insertion may be performed in an iterative fashion to insert into different data signals the desired number of errors, wherein the errors are placed within the code words of the data signals at different location permutations for each data signal. In one implementation, error verification is performed using an error accumulator located in the receiver, and means are provided for examining an error accumulator count of the error accumulator to see if the number of accumulated errors matches with the number of inserted errors.
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fullrecord <record><control><sourceid>uspatents_EFH</sourceid><recordid>TN_cdi_uspatents_grants_06983414</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>06983414</sourcerecordid><originalsourceid>FETCH-uspatents_grants_069834143</originalsourceid><addsrcrecordid>eNrjZLByLSrKL1LIzCtOLSrJzM9TSM4sSi7NLFFIA4oG-_u5hoBY5YlFKQqpYJXJ-UVFqckgpTwMrGmJOcWpvFCam0HBzTXE2UO3tLggsSQ1r6Q4Pr0oEUQZmFlaGJsYmhgToQQAQYkv9A</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Error insertion circuit for SONET forward error correction</title><source>USPTO Issued Patents</source><creator>Duschatko, Douglas E ; Thurston, Andrew J</creator><creatorcontrib>Duschatko, Douglas E ; Thurston, Andrew J ; Cisco Technology, Inc</creatorcontrib><description>An OC-192 front-end application-specific integrated circuit (ASIC) de-interleaves an OC-192 signal to create four OC-48 signals, and decodes error-correction codes embedded in each of the four OC-48 signals. An error insertion circuit is also provided for verifying correct operation of encoding and decoding circuits. A desired number of errors may be programmed for insertion into the OC-48 data signals. Error insertion may be performed in an iterative fashion to insert into different data signals the desired number of errors, wherein the errors are placed within the code words of the data signals at different location permutations for each data signal. In one implementation, error verification is performed using an error accumulator located in the receiver, and means are provided for examining an error accumulator count of the error accumulator to see if the number of accumulated errors matches with the number of inserted errors.</description><language>eng</language><creationdate>2006</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6983414$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,776,798,881,64012</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6983414$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Duschatko, Douglas E</creatorcontrib><creatorcontrib>Thurston, Andrew J</creatorcontrib><creatorcontrib>Cisco Technology, Inc</creatorcontrib><title>Error insertion circuit for SONET forward error correction</title><description>An OC-192 front-end application-specific integrated circuit (ASIC) de-interleaves an OC-192 signal to create four OC-48 signals, and decodes error-correction codes embedded in each of the four OC-48 signals. An error insertion circuit is also provided for verifying correct operation of encoding and decoding circuits. A desired number of errors may be programmed for insertion into the OC-48 data signals. Error insertion may be performed in an iterative fashion to insert into different data signals the desired number of errors, wherein the errors are placed within the code words of the data signals at different location permutations for each data signal. In one implementation, error verification is performed using an error accumulator located in the receiver, and means are provided for examining an error accumulator count of the error accumulator to see if the number of accumulated errors matches with the number of inserted errors.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2006</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNrjZLByLSrKL1LIzCtOLSrJzM9TSM4sSi7NLFFIA4oG-_u5hoBY5YlFKQqpYJXJ-UVFqckgpTwMrGmJOcWpvFCam0HBzTXE2UO3tLggsSQ1r6Q4Pr0oEUQZmFlaGJsYmhgToQQAQYkv9A</recordid><startdate>20060103</startdate><enddate>20060103</enddate><creator>Duschatko, Douglas E</creator><creator>Thurston, Andrew J</creator><scope>EFH</scope></search><sort><creationdate>20060103</creationdate><title>Error insertion circuit for SONET forward error correction</title><author>Duschatko, Douglas E ; Thurston, Andrew J</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_069834143</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2006</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Duschatko, Douglas E</creatorcontrib><creatorcontrib>Thurston, Andrew J</creatorcontrib><creatorcontrib>Cisco Technology, Inc</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Duschatko, Douglas E</au><au>Thurston, Andrew J</au><aucorp>Cisco Technology, Inc</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Error insertion circuit for SONET forward error correction</title><date>2006-01-03</date><risdate>2006</risdate><abstract>An OC-192 front-end application-specific integrated circuit (ASIC) de-interleaves an OC-192 signal to create four OC-48 signals, and decodes error-correction codes embedded in each of the four OC-48 signals. An error insertion circuit is also provided for verifying correct operation of encoding and decoding circuits. A desired number of errors may be programmed for insertion into the OC-48 data signals. Error insertion may be performed in an iterative fashion to insert into different data signals the desired number of errors, wherein the errors are placed within the code words of the data signals at different location permutations for each data signal. In one implementation, error verification is performed using an error accumulator located in the receiver, and means are provided for examining an error accumulator count of the error accumulator to see if the number of accumulated errors matches with the number of inserted errors.</abstract><oa>free_for_read</oa></addata></record>
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title Error insertion circuit for SONET forward error correction
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-12T05%3A07%3A37IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-uspatents_EFH&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Duschatko,%20Douglas%20E&rft.aucorp=Cisco%20Technology,%20Inc&rft.date=2006-01-03&rft_id=info:doi/&rft_dat=%3Cuspatents_EFH%3E06983414%3C/uspatents_EFH%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true