Semiconductor devices and methods for fabricating the same

Semiconductor devices and methods for fabricating the same include a device isolation layer formed at a predetermined region of a semiconductor substrate to define a cell active region, a resistor active region, and an MROM active region. The device further includes a floating junction region, a res...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
1. Verfasser: Park, Weon-Ho
Format: Patent
Sprache:eng
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator Park, Weon-Ho
description Semiconductor devices and methods for fabricating the same include a device isolation layer formed at a predetermined region of a semiconductor substrate to define a cell active region, a resistor active region, and an MROM active region. The device further includes a floating junction region, a resistive junction region, and a channel junction region, which are formed in the cell active region, the resistor active region, and the MROM active region, respectively. The floating junction region, the resistive junction region, and the channel junction region have the same thickness. A covering gate and an MROM gate cross over the resistive active region and the channel active region, respectively. Also, a memory gate and a select gate cross over the cell active region. The method includes forming a device isolation layer at a predetermined region of a semiconductor substrate to define a cell active region, a resistor active region, and an MROM active region. A floating junction region, a resistive junction region, and a channel junction region are then formed in the cell active region, the resistor active region, and the MROM active region, respectively. Thereafter, a select gate and a memory gate are formed on the cell active region. Also, a covering gate and an MROM gate are formed on the resistor active region and the MROM active region, respectively. The floating junction region, the resistive junction region, and the channel junction region are preferably formed at the same time.
format Patent
fullrecord <record><control><sourceid>uspatents_EFH</sourceid><recordid>TN_cdi_uspatents_grants_06967388</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>06967388</sourcerecordid><originalsourceid>FETCH-uspatents_grants_069673883</originalsourceid><addsrcrecordid>eNrjZLAKTs3NTM7PSylNLskvUkhJLctMTi1WSMxLUchNLcnITylWSAOKpyUmFWUmJ5Zk5qUrlGSkKhQn5qbyMLCmJeYUp_JCaW4GBTfXEGcP3dLigsSS1LyS4vj0okQQZWBmaWZubGFhTIQSAFeCMB4</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Semiconductor devices and methods for fabricating the same</title><source>USPTO Issued Patents</source><creator>Park, Weon-Ho</creator><creatorcontrib>Park, Weon-Ho ; Samsung Electronics Co., Ltd</creatorcontrib><description>Semiconductor devices and methods for fabricating the same include a device isolation layer formed at a predetermined region of a semiconductor substrate to define a cell active region, a resistor active region, and an MROM active region. The device further includes a floating junction region, a resistive junction region, and a channel junction region, which are formed in the cell active region, the resistor active region, and the MROM active region, respectively. The floating junction region, the resistive junction region, and the channel junction region have the same thickness. A covering gate and an MROM gate cross over the resistive active region and the channel active region, respectively. Also, a memory gate and a select gate cross over the cell active region. The method includes forming a device isolation layer at a predetermined region of a semiconductor substrate to define a cell active region, a resistor active region, and an MROM active region. A floating junction region, a resistive junction region, and a channel junction region are then formed in the cell active region, the resistor active region, and the MROM active region, respectively. Thereafter, a select gate and a memory gate are formed on the cell active region. Also, a covering gate and an MROM gate are formed on the resistor active region and the MROM active region, respectively. The floating junction region, the resistive junction region, and the channel junction region are preferably formed at the same time.</description><language>eng</language><creationdate>2005</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6967388$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,776,798,881,64012</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6967388$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Park, Weon-Ho</creatorcontrib><creatorcontrib>Samsung Electronics Co., Ltd</creatorcontrib><title>Semiconductor devices and methods for fabricating the same</title><description>Semiconductor devices and methods for fabricating the same include a device isolation layer formed at a predetermined region of a semiconductor substrate to define a cell active region, a resistor active region, and an MROM active region. The device further includes a floating junction region, a resistive junction region, and a channel junction region, which are formed in the cell active region, the resistor active region, and the MROM active region, respectively. The floating junction region, the resistive junction region, and the channel junction region have the same thickness. A covering gate and an MROM gate cross over the resistive active region and the channel active region, respectively. Also, a memory gate and a select gate cross over the cell active region. The method includes forming a device isolation layer at a predetermined region of a semiconductor substrate to define a cell active region, a resistor active region, and an MROM active region. A floating junction region, a resistive junction region, and a channel junction region are then formed in the cell active region, the resistor active region, and the MROM active region, respectively. Thereafter, a select gate and a memory gate are formed on the cell active region. Also, a covering gate and an MROM gate are formed on the resistor active region and the MROM active region, respectively. The floating junction region, the resistive junction region, and the channel junction region are preferably formed at the same time.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2005</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNrjZLAKTs3NTM7PSylNLskvUkhJLctMTi1WSMxLUchNLcnITylWSAOKpyUmFWUmJ5Zk5qUrlGSkKhQn5qbyMLCmJeYUp_JCaW4GBTfXEGcP3dLigsSS1LyS4vj0okQQZWBmaWZubGFhTIQSAFeCMB4</recordid><startdate>20051122</startdate><enddate>20051122</enddate><creator>Park, Weon-Ho</creator><scope>EFH</scope></search><sort><creationdate>20051122</creationdate><title>Semiconductor devices and methods for fabricating the same</title><author>Park, Weon-Ho</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_069673883</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2005</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Park, Weon-Ho</creatorcontrib><creatorcontrib>Samsung Electronics Co., Ltd</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Park, Weon-Ho</au><aucorp>Samsung Electronics Co., Ltd</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Semiconductor devices and methods for fabricating the same</title><date>2005-11-22</date><risdate>2005</risdate><abstract>Semiconductor devices and methods for fabricating the same include a device isolation layer formed at a predetermined region of a semiconductor substrate to define a cell active region, a resistor active region, and an MROM active region. The device further includes a floating junction region, a resistive junction region, and a channel junction region, which are formed in the cell active region, the resistor active region, and the MROM active region, respectively. The floating junction region, the resistive junction region, and the channel junction region have the same thickness. A covering gate and an MROM gate cross over the resistive active region and the channel active region, respectively. Also, a memory gate and a select gate cross over the cell active region. The method includes forming a device isolation layer at a predetermined region of a semiconductor substrate to define a cell active region, a resistor active region, and an MROM active region. A floating junction region, a resistive junction region, and a channel junction region are then formed in the cell active region, the resistor active region, and the MROM active region, respectively. Thereafter, a select gate and a memory gate are formed on the cell active region. Also, a covering gate and an MROM gate are formed on the resistor active region and the MROM active region, respectively. The floating junction region, the resistive junction region, and the channel junction region are preferably formed at the same time.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_uspatents_grants_06967388
source USPTO Issued Patents
title Semiconductor devices and methods for fabricating the same
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-03T20%3A13%3A56IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-uspatents_EFH&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Park,%20Weon-Ho&rft.aucorp=Samsung%20Electronics%20Co.,%20Ltd&rft.date=2005-11-22&rft_id=info:doi/&rft_dat=%3Cuspatents_EFH%3E06967388%3C/uspatents_EFH%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true