Method and apparatus for implementing two-tiered thread state multithreading support with high clock rate

Method and apparatus for implementing two-tiered thread state multithreading support with high clock rate

A method and apparatus are provided for implementing two-tiered thread state multithreading support with a high clock rate. A first tier thread state storage stores a limited number of runnable thread register states. The limited number is less than a threshold value. Next thread selection logic cou...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Kossman, Harold F, Mullins, Timothy John
Format: Patent
Sprache:eng
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator Kossman, Harold F
Mullins, Timothy John
description A method and apparatus are provided for implementing two-tiered thread state multithreading support with a high clock rate. A first tier thread state storage stores a limited number of runnable thread register states. The limited number is less than a threshold value. Next thread selection logic coupled between the first tier thread state storage and a currently executing processor state, picks a next thread to run on a processor from the limited number of runnable thread register states. A second tier thread storage facility stores a second number of thread states that is greater than the limited number of runnable thread register states. A runnable thread selection logic coupled between the first tier thread state storage and the second tier thread storage facility, selectively exchanges thread states between the first tier limited number of runnable thread register states and the second tier thread storage facility.
format Patent
fullrecord <record><control><sourceid>uspatents_EFH</sourceid><recordid>TN_cdi_uspatents_grants_06965986</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>06965986</sourcerecordid><originalsourceid>FETCH-uspatents_grants_069659863</originalsourceid><addsrcrecordid>eNqNjE0KwjAQhbtxIeod5gIFQQx2LRU37tzL0EyTwfyRTOj1TdEDuHh88N7H23b8ILFRA4aWlDCj1AJzzMA-OfIUhIMBWWIvTJk0iM2EGoqgEPjqhL_NqpWaUswCS-vAsrEwuTi9ob3SvtvM6Aodftx1cBuf13tfS2pzkPIyGVcc1aDOw0Wd_lA-UbZCZA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method and apparatus for implementing two-tiered thread state multithreading support with high clock rate</title><source>USPTO Issued Patents</source><creator>Kossman, Harold F ; Mullins, Timothy John</creator><creatorcontrib>Kossman, Harold F ; Mullins, Timothy John ; International Business Machines Corporation</creatorcontrib><description>A method and apparatus are provided for implementing two-tiered thread state multithreading support with a high clock rate. A first tier thread state storage stores a limited number of runnable thread register states. The limited number is less than a threshold value. Next thread selection logic coupled between the first tier thread state storage and a currently executing processor state, picks a next thread to run on a processor from the limited number of runnable thread register states. A second tier thread storage facility stores a second number of thread states that is greater than the limited number of runnable thread register states. A runnable thread selection logic coupled between the first tier thread state storage and the second tier thread storage facility, selectively exchanges thread states between the first tier limited number of runnable thread register states and the second tier thread storage facility.</description><language>eng</language><creationdate>2005</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6965986$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,776,798,881,64015</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6965986$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Kossman, Harold F</creatorcontrib><creatorcontrib>Mullins, Timothy John</creatorcontrib><creatorcontrib>International Business Machines Corporation</creatorcontrib><title>Method and apparatus for implementing two-tiered thread state multithreading support with high clock rate</title><description>A method and apparatus are provided for implementing two-tiered thread state multithreading support with a high clock rate. A first tier thread state storage stores a limited number of runnable thread register states. The limited number is less than a threshold value. Next thread selection logic coupled between the first tier thread state storage and a currently executing processor state, picks a next thread to run on a processor from the limited number of runnable thread register states. A second tier thread storage facility stores a second number of thread states that is greater than the limited number of runnable thread register states. A runnable thread selection logic coupled between the first tier thread state storage and the second tier thread storage facility, selectively exchanges thread states between the first tier limited number of runnable thread register states and the second tier thread storage facility.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2005</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNqNjE0KwjAQhbtxIeod5gIFQQx2LRU37tzL0EyTwfyRTOj1TdEDuHh88N7H23b8ILFRA4aWlDCj1AJzzMA-OfIUhIMBWWIvTJk0iM2EGoqgEPjqhL_NqpWaUswCS-vAsrEwuTi9ob3SvtvM6Aodftx1cBuf13tfS2pzkPIyGVcc1aDOw0Wd_lA-UbZCZA</recordid><startdate>20051115</startdate><enddate>20051115</enddate><creator>Kossman, Harold F</creator><creator>Mullins, Timothy John</creator><scope>EFH</scope></search><sort><creationdate>20051115</creationdate><title>Method and apparatus for implementing two-tiered thread state multithreading support with high clock rate</title><author>Kossman, Harold F ; Mullins, Timothy John</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_069659863</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2005</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Kossman, Harold F</creatorcontrib><creatorcontrib>Mullins, Timothy John</creatorcontrib><creatorcontrib>International Business Machines Corporation</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Kossman, Harold F</au><au>Mullins, Timothy John</au><aucorp>International Business Machines Corporation</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method and apparatus for implementing two-tiered thread state multithreading support with high clock rate</title><date>2005-11-15</date><risdate>2005</risdate><abstract>A method and apparatus are provided for implementing two-tiered thread state multithreading support with a high clock rate. A first tier thread state storage stores a limited number of runnable thread register states. The limited number is less than a threshold value. Next thread selection logic coupled between the first tier thread state storage and a currently executing processor state, picks a next thread to run on a processor from the limited number of runnable thread register states. A second tier thread storage facility stores a second number of thread states that is greater than the limited number of runnable thread register states. A runnable thread selection logic coupled between the first tier thread state storage and the second tier thread storage facility, selectively exchanges thread states between the first tier limited number of runnable thread register states and the second tier thread storage facility.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_uspatents_grants_06965986
source USPTO Issued Patents
title Method and apparatus for implementing two-tiered thread state multithreading support with high clock rate
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-23T22%3A14%3A24IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-uspatents_EFH&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Kossman,%20Harold%20F&rft.aucorp=International%20Business%20Machines%20Corporation&rft.date=2005-11-15&rft_id=info:doi/&rft_dat=%3Cuspatents_EFH%3E06965986%3C/uspatents_EFH%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true