Padless structure design for easy identification of bridging defects in lines by passive voltage contrast
A new test structure to locate bridging defects in a conductive layer of an integrated circuit device is achieved. The test structure comprises a line comprising a conductive layer overlying a substrate. The line is coupled to ground. A plurality of rectangles comprises the conductive layer. The rec...
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creator | Song, Zhigang Redkar, Shailesh Oh, Chong Khiam |
description | A new test structure to locate bridging defects in a conductive layer of an integrated circuit device is achieved. The test structure comprises a line comprising a conductive layer overlying a substrate. The line is coupled to ground. A plurality of rectangles comprises the conductive layer. The rectangles are not connected to the line or to other rectangles. Near edges of the rectangles and of the line are parallel. The rectangles are floating. The test structure is used with a passive voltage contrast test in a scanning electron microscope. A test structure and method to measure critical dimensions is disclosed. |
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The test structure comprises a line comprising a conductive layer overlying a substrate. The line is coupled to ground. A plurality of rectangles comprises the conductive layer. The rectangles are not connected to the line or to other rectangles. Near edges of the rectangles and of the line are parallel. The rectangles are floating. The test structure is used with a passive voltage contrast test in a scanning electron microscope. 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The test structure comprises a line comprising a conductive layer overlying a substrate. The line is coupled to ground. A plurality of rectangles comprises the conductive layer. The rectangles are not connected to the line or to other rectangles. Near edges of the rectangles and of the line are parallel. The rectangles are floating. The test structure is used with a passive voltage contrast test in a scanning electron microscope. A test structure and method to measure critical dimensions is disclosed.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2005</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNqNzTEKwkAQRuE0FqLe4b-AIKiR1KJYWtjLZHd2GVh2w84kkNsbwQNYveaDt27kST6xKtTq6GysDM8qMSOUCiadIZ6zSRBHJiWjBPRVfJQcFxrYmUIykmRW9DMGUpWJMZVkFBmuZKuktm1WgZLy7tdNg_vtdX3sRx3IloW-Y6VvDm136i7t-fgH-QA75UI1</recordid><startdate>20050927</startdate><enddate>20050927</enddate><creator>Song, Zhigang</creator><creator>Redkar, Shailesh</creator><creator>Oh, Chong Khiam</creator><scope>EFH</scope></search><sort><creationdate>20050927</creationdate><title>Padless structure design for easy identification of bridging defects in lines by passive voltage contrast</title><author>Song, Zhigang ; Redkar, Shailesh ; Oh, Chong Khiam</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_069497653</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2005</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Song, Zhigang</creatorcontrib><creatorcontrib>Redkar, Shailesh</creatorcontrib><creatorcontrib>Oh, Chong Khiam</creatorcontrib><creatorcontrib>Chartered Semiconductor Manufacturing Ltd</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Song, Zhigang</au><au>Redkar, Shailesh</au><au>Oh, Chong Khiam</au><aucorp>Chartered Semiconductor Manufacturing Ltd</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Padless structure design for easy identification of bridging defects in lines by passive voltage contrast</title><date>2005-09-27</date><risdate>2005</risdate><abstract>A new test structure to locate bridging defects in a conductive layer of an integrated circuit device is achieved. The test structure comprises a line comprising a conductive layer overlying a substrate. The line is coupled to ground. A plurality of rectangles comprises the conductive layer. The rectangles are not connected to the line or to other rectangles. Near edges of the rectangles and of the line are parallel. The rectangles are floating. The test structure is used with a passive voltage contrast test in a scanning electron microscope. A test structure and method to measure critical dimensions is disclosed.</abstract><oa>free_for_read</oa></addata></record> |
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title | Padless structure design for easy identification of bridging defects in lines by passive voltage contrast |
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