Methods of resource optimization in programmable logic devices to reduce test time

Methods of optimizing the use of routing resources in programmable logic devices (PLDs) to minimize test time. A set of routing resources is identified that are not used in most designs, and a device model is provided to the user that prevents the use of these resources. Because the routing resource...

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Bibliographische Detailangaben

Hauptverfasser:	Lai, Andrew W, Simmons, Randy J, Mansour, Teymour M, Tong, Vincent L, Lindholm, Jeffrey V, Young, Jay T, Troxel, William R, Krishnamurthy, Sridhar
Format:	Patent
Sprache:	eng
Online-Zugang:	Volltext bestellen
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