Feature targeted inspection

Feature targeted inspection

A method of inspecting a subject integrated circuit. A set of historical integrated circuits is inspected to detect defects and produce historical data. Features of the historical integrated circuits that have an occurrence of defects that is greater than a given limit are designated as high risk fe...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
1. Verfasser: Madge, Robert
Format: Patent
Sprache:eng
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator Madge, Robert
description A method of inspecting a subject integrated circuit. A set of historical integrated circuits is inspected to detect defects and produce historical data. Features of the historical integrated circuits that have an occurrence of defects that is greater than a given limit are designated as high risk features, based on the historical data. Locations of the high risk features are identified on the subject integrated circuit. The locations of the high risk features are input into an inspection tool, and the locations of the high risk features on the integrated circuit are inspected to at least one of detect defects and measure critical dimensions, and produce subject data.
format Patent
fullrecord <record><control><sourceid>uspatents_EFH</sourceid><recordid>TN_cdi_uspatents_grants_06931297</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>06931297</sourcerecordid><originalsourceid>FETCH-uspatents_grants_069312973</originalsourceid><addsrcrecordid>eNrjZJB2S00sKS1KVShJLEpPLUlNUcjMKy5ITS7JzM_jYWBNS8wpTuWF0twMCm6uIc4euqXFBYklqXklxfHpRYkgysDM0tjQyNLcmAglAHGPJJI</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Feature targeted inspection</title><source>USPTO Issued Patents</source><creator>Madge, Robert</creator><creatorcontrib>Madge, Robert ; LSI Logic Corporation</creatorcontrib><description>A method of inspecting a subject integrated circuit. A set of historical integrated circuits is inspected to detect defects and produce historical data. Features of the historical integrated circuits that have an occurrence of defects that is greater than a given limit are designated as high risk features, based on the historical data. Locations of the high risk features are identified on the subject integrated circuit. The locations of the high risk features are input into an inspection tool, and the locations of the high risk features on the integrated circuit are inspected to at least one of detect defects and measure critical dimensions, and produce subject data.</description><language>eng</language><creationdate>2005</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6931297$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,776,798,881,64015</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6931297$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Madge, Robert</creatorcontrib><creatorcontrib>LSI Logic Corporation</creatorcontrib><title>Feature targeted inspection</title><description>A method of inspecting a subject integrated circuit. A set of historical integrated circuits is inspected to detect defects and produce historical data. Features of the historical integrated circuits that have an occurrence of defects that is greater than a given limit are designated as high risk features, based on the historical data. Locations of the high risk features are identified on the subject integrated circuit. The locations of the high risk features are input into an inspection tool, and the locations of the high risk features on the integrated circuit are inspected to at least one of detect defects and measure critical dimensions, and produce subject data.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2005</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNrjZJB2S00sKS1KVShJLEpPLUlNUcjMKy5ITS7JzM_jYWBNS8wpTuWF0twMCm6uIc4euqXFBYklqXklxfHpRYkgysDM0tjQyNLcmAglAHGPJJI</recordid><startdate>20050816</startdate><enddate>20050816</enddate><creator>Madge, Robert</creator><scope>EFH</scope></search><sort><creationdate>20050816</creationdate><title>Feature targeted inspection</title><author>Madge, Robert</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_069312973</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2005</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Madge, Robert</creatorcontrib><creatorcontrib>LSI Logic Corporation</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Madge, Robert</au><aucorp>LSI Logic Corporation</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Feature targeted inspection</title><date>2005-08-16</date><risdate>2005</risdate><abstract>A method of inspecting a subject integrated circuit. A set of historical integrated circuits is inspected to detect defects and produce historical data. Features of the historical integrated circuits that have an occurrence of defects that is greater than a given limit are designated as high risk features, based on the historical data. Locations of the high risk features are identified on the subject integrated circuit. The locations of the high risk features are input into an inspection tool, and the locations of the high risk features on the integrated circuit are inspected to at least one of detect defects and measure critical dimensions, and produce subject data.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_uspatents_grants_06931297
source USPTO Issued Patents
title Feature targeted inspection
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-28T00%3A36%3A06IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-uspatents_EFH&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Madge,%20Robert&rft.aucorp=LSI%20Logic%20Corporation&rft.date=2005-08-16&rft_id=info:doi/&rft_dat=%3Cuspatents_EFH%3E06931297%3C/uspatents_EFH%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true