Macro design techniques to accommodate chip level wiring and circuit placement across the macro

Macro design techniques are disclosed for facilitating subsequent stage wiring across the macro. Whitespace areas within the macro are rearranged to accommodate the wiring. The rearrangement may take the form of physical rearrangement of the whitespace areas into routing tracks extending from one si...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Bednar, Thomas R, Dunn, Paul E, Gould, Scott W, Panner, Jeannie H, Zuchowski, Paul S
Format:	Patent
Sprache:	eng
Online-Zugang:	Volltext bestellen
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