System and method for generating a mask layout file to reduce power supply voltage fluctuations in an integrated circuit
A system and method for generating a mask layout file to reduce power supply voltage fluctuations in an integrated circuit are disclosed. The method includes analyzing a pattern in a mask layout file to identify a region in the pattern to add one or more decoupling capacitors. Once the region is ide...
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| Format: | Patent |
| Sprache: | eng |
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