Method and apparatus for invalidating a cache line without data return in a multi-node architecture

Embodiments of the present invention relate to a computer system having a multi-node computer architecture. In particular, the present invention relates to a method and apparatus for invalidating cache lines in a multi-node architecture. A method of invalidating a cache line in a system having a plu...

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Bibliographische Detailangaben

Hauptverfasser:	Khare, Manoj, Kumar, Akhilesh, Creta, Ken, Looi, Lily P, George, Robert T, Cekleov, Michel
Format:	Patent
Sprache:	eng
Online-Zugang:	Volltext bestellen
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