Bit line selection circuit having hierarchical structure

1. Field of the Invention Disclosed is a bit line selection circuit having hierarchical structure capable of preventing delay of operation speed due to signal loading by selecting a bit line with a sub bit line selection driver in a hierarchically shared bit line sense amp. The disclosed comprises:...

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Bibliographische Detailangaben

1. Verfasser:	Hong, Jong Hoon
Format:	Patent
Sprache:	eng
Online-Zugang:	Volltext bestellen
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