Integrated circuit structure

Integrated circuit structure

1. Technical Field A semiconductor chip carrier having an increased chip connector and plated through hole density. In particular, a substrate having a plurality of plated through holes therein, and a fatigue resistant redistribution layer thereon. The redistribution layer includes a plurality of vi...

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Hauptverfasser: Alcoe, David J, Downes, Jr., Francis J, Jones, Gerald W, Kresge, John S, Tytran-Palomaki, Cheryl L
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Sprache:eng
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creator Alcoe, David J
Downes, Jr., Francis J
Jones, Gerald W
Kresge, John S
Tytran-Palomaki, Cheryl L
description 1. Technical Field A semiconductor chip carrier having an increased chip connector and plated through hole density. In particular, a substrate having a plurality of plated through holes therein, and a fatigue resistant redistribution layer thereon. The redistribution layer includes a plurality of vias selectively positioned over and contacting the plated through holes. The substrate further including a ground plane, two pair of signal planes, and two pair of power planes, wherein the second pair of power planes are located directly underneath the external dielectric layer. A buried plated through hole within the substrate.
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Technical Field A semiconductor chip carrier having an increased chip connector and plated through hole density. In particular, a substrate having a plurality of plated through holes therein, and a fatigue resistant redistribution layer thereon. The redistribution layer includes a plurality of vias selectively positioned over and contacting the plated through holes. The substrate further including a ground plane, two pair of signal planes, and two pair of power planes, wherein the second pair of power planes are located directly underneath the external dielectric layer. A buried plated through hole within the substrate.</abstract><oa>free_for_read</oa></addata></record>
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title Integrated circuit structure
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