Method and circuit for reducing the power up time of a phase lock loop

The present invention relates to the field of phase lock loops. Specifically, the present invention relates to a method for reducing the power up time of a phase lock loop. A method and circuit for reducing the power up time of a phase lock loop (PLL). In one embodiment, the present invention cuts off a first voltage to the phase lock loop thereby powering down the phase lock loop. In power down, a second voltage is utilized to maintain the power requirements of the filter node within the phase lock loop while the other components of the phase lock loop are powered down. The PLL is now in a power down mode. The present invention then restores the first voltage to the PLL. Once the internal components of the PLL stabilize, the second voltage is disengaged from the filter node wherein the phase lock loop is powered up to operational power.