Circuit and method for prefetching data for a texture cache

The present invention relates in general to graphics systems, and in particular to methods and apparatus for prefetching cache lines in a graphics system. A cache memory apparatus for graphics and other systems. The cache memory apparatus includes a cache memory having a first number of cache lines,...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Minkin, Alexander L, Rubinstein, Oren
Format: Patent
Sprache:eng
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator Minkin, Alexander L
Rubinstein, Oren
description The present invention relates in general to graphics systems, and in particular to methods and apparatus for prefetching cache lines in a graphics system. A cache memory apparatus for graphics and other systems. The cache memory apparatus includes a cache memory having a first number of cache lines, each cache line addressable by a cache line address; a first plurality of storage elements coupled to a first address bus; and a second plurality of storage elements coupled to the first plurality of storage elements. The first plurality of storage elements holds a second number of cache line addresses, and the second plurality of storage elements holds a third number of cache line addresses.
format Patent
fullrecord <record><control><sourceid>uspatents_EFH</sourceid><recordid>TN_cdi_uspatents_grants_06629188</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>06629188</sourcerecordid><originalsourceid>FETCH-uspatents_grants_066291883</originalsourceid><addsrcrecordid>eNrjZLB2zixKLs0sUUjMS1HITS3JyE9RSMsvUigoSk1LLUnOyMxLV0hJLEkECyYqlKRWlJQWpSokJyZnpPIwsKYl5hSn8kJpbgYFN9cQZw_d0uKCxJLUvJLi-PSiRBBlYGZmZGloYWFMhBIARqcv5A</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Circuit and method for prefetching data for a texture cache</title><source>USPTO Issued Patents</source><creator>Minkin, Alexander L ; Rubinstein, Oren</creator><creatorcontrib>Minkin, Alexander L ; Rubinstein, Oren ; Nvidia Corporation</creatorcontrib><description>The present invention relates in general to graphics systems, and in particular to methods and apparatus for prefetching cache lines in a graphics system. A cache memory apparatus for graphics and other systems. The cache memory apparatus includes a cache memory having a first number of cache lines, each cache line addressable by a cache line address; a first plurality of storage elements coupled to a first address bus; and a second plurality of storage elements coupled to the first plurality of storage elements. The first plurality of storage elements holds a second number of cache line addresses, and the second plurality of storage elements holds a third number of cache line addresses.</description><language>eng</language><creationdate>2003</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6629188$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,778,800,883,64020</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6629188$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Minkin, Alexander L</creatorcontrib><creatorcontrib>Rubinstein, Oren</creatorcontrib><creatorcontrib>Nvidia Corporation</creatorcontrib><title>Circuit and method for prefetching data for a texture cache</title><description>The present invention relates in general to graphics systems, and in particular to methods and apparatus for prefetching cache lines in a graphics system. A cache memory apparatus for graphics and other systems. The cache memory apparatus includes a cache memory having a first number of cache lines, each cache line addressable by a cache line address; a first plurality of storage elements coupled to a first address bus; and a second plurality of storage elements coupled to the first plurality of storage elements. The first plurality of storage elements holds a second number of cache line addresses, and the second plurality of storage elements holds a third number of cache line addresses.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2003</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNrjZLB2zixKLs0sUUjMS1HITS3JyE9RSMsvUigoSk1LLUnOyMxLV0hJLEkECyYqlKRWlJQWpSokJyZnpPIwsKYl5hSn8kJpbgYFN9cQZw_d0uKCxJLUvJLi-PSiRBBlYGZmZGloYWFMhBIARqcv5A</recordid><startdate>20030930</startdate><enddate>20030930</enddate><creator>Minkin, Alexander L</creator><creator>Rubinstein, Oren</creator><scope>EFH</scope></search><sort><creationdate>20030930</creationdate><title>Circuit and method for prefetching data for a texture cache</title><author>Minkin, Alexander L ; Rubinstein, Oren</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_066291883</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2003</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Minkin, Alexander L</creatorcontrib><creatorcontrib>Rubinstein, Oren</creatorcontrib><creatorcontrib>Nvidia Corporation</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Minkin, Alexander L</au><au>Rubinstein, Oren</au><aucorp>Nvidia Corporation</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Circuit and method for prefetching data for a texture cache</title><date>2003-09-30</date><risdate>2003</risdate><abstract>The present invention relates in general to graphics systems, and in particular to methods and apparatus for prefetching cache lines in a graphics system. A cache memory apparatus for graphics and other systems. The cache memory apparatus includes a cache memory having a first number of cache lines, each cache line addressable by a cache line address; a first plurality of storage elements coupled to a first address bus; and a second plurality of storage elements coupled to the first plurality of storage elements. The first plurality of storage elements holds a second number of cache line addresses, and the second plurality of storage elements holds a third number of cache line addresses.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_uspatents_grants_06629188
source USPTO Issued Patents
title Circuit and method for prefetching data for a texture cache
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-17T04%3A11%3A51IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-uspatents_EFH&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Minkin,%20Alexander%20L&rft.aucorp=Nvidia%20Corporation&rft.date=2003-09-30&rft_id=info:doi/&rft_dat=%3Cuspatents_EFH%3E06629188%3C/uspatents_EFH%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true