FPGA lookup table with high speed read decorder

The present invention relates to programmable logic devices, and more particularly to lookup tables utilized in programmable logic devices. A fast, space-efficient lookup table (LUT) for programmable logic devices (PLDs) in which the write decoder, read decoder and memory block of the LUT are modifi...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Carberry, Richard A, Young, Steven P, Bauer, Trevor J
Format:	Patent
Sprache:	eng
Online-Zugang:	Volltext bestellen
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