Mask programmed ROM inviolable by reverse engineering inspections and method of fabrication
The present invention relates in general to integrated circuits, and in particular, to a read only memory (ROM) device. A read only memory (ROM) device includes a semiconductor substrate having a first type of conductivity, and a plurality of memory cells on the semiconductor substrate. Each memory...
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creator | Vajana, Bruno Patelmo, Matteo |
description | The present invention relates in general to integrated circuits, and in particular, to a read only memory (ROM) device.
A read only memory (ROM) device includes a semiconductor substrate having a first type of conductivity, and a plurality of memory cells on the semiconductor substrate. Each memory cell includes first and second regions of a second conductivity type opposite the first conductivity type. A first dielectric layer is on the plurality of memory cells, and a plurality of first contacts extend through the first dielectric layer for contacting the first regions. A second dielectric layer is on the first dielectric layer and the plurality of first contacts. A plurality of second contacts extend through the second dielectric layer and overlie the corresponding second regions. The plurality of second contacts define interconnection contacts by further extending through the first dielectric layer for contacting the second regions for memory cells programmed in a conductive state, and false interconnection contacts by not extending through the first dielectric layer for contacting the second regions for memory cells programmed in a non-conductive state. |
format | Patent |
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A read only memory (ROM) device includes a semiconductor substrate having a first type of conductivity, and a plurality of memory cells on the semiconductor substrate. Each memory cell includes first and second regions of a second conductivity type opposite the first conductivity type. A first dielectric layer is on the plurality of memory cells, and a plurality of first contacts extend through the first dielectric layer for contacting the first regions. A second dielectric layer is on the first dielectric layer and the plurality of first contacts. A plurality of second contacts extend through the second dielectric layer and overlie the corresponding second regions. The plurality of second contacts define interconnection contacts by further extending through the first dielectric layer for contacting the second regions for memory cells programmed in a conductive state, and false interconnection contacts by not extending through the first dielectric layer for contacting the second regions for memory cells programmed in a non-conductive state.</description><language>eng</language><creationdate>2003</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6614080$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,776,798,881,64012</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6614080$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Vajana, Bruno</creatorcontrib><creatorcontrib>Patelmo, Matteo</creatorcontrib><creatorcontrib>STMicroelectronics S.r.l</creatorcontrib><title>Mask programmed ROM inviolable by reverse engineering inspections and method of fabrication</title><description>The present invention relates in general to integrated circuits, and in particular, to a read only memory (ROM) device.
A read only memory (ROM) device includes a semiconductor substrate having a first type of conductivity, and a plurality of memory cells on the semiconductor substrate. Each memory cell includes first and second regions of a second conductivity type opposite the first conductivity type. A first dielectric layer is on the plurality of memory cells, and a plurality of first contacts extend through the first dielectric layer for contacting the first regions. A second dielectric layer is on the first dielectric layer and the plurality of first contacts. A plurality of second contacts extend through the second dielectric layer and overlie the corresponding second regions. The plurality of second contacts define interconnection contacts by further extending through the first dielectric layer for contacting the second regions for memory cells programmed in a conductive state, and false interconnection contacts by not extending through the first dielectric layer for contacting the second regions for memory cells programmed in a non-conductive state.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2003</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNqNjTEKAjEQANNYiPqH_YAQUQ57UWwOQewsZHO3icFkE7LxwN97Bz7AaooZmLm6tygvyCW5gjFSD9dLC54HnwKaQGA-UGigIgTEzjNR8ezGQjJ11ScWQO4hUn2mHpIFi6b4Die1VDOLQWj140LB6Xg7nNdvyViJqzzG6wTdNJud3uvtH8kXJaU8aw</recordid><startdate>20030902</startdate><enddate>20030902</enddate><creator>Vajana, Bruno</creator><creator>Patelmo, Matteo</creator><scope>EFH</scope></search><sort><creationdate>20030902</creationdate><title>Mask programmed ROM inviolable by reverse engineering inspections and method of fabrication</title><author>Vajana, Bruno ; Patelmo, Matteo</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_066140803</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2003</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Vajana, Bruno</creatorcontrib><creatorcontrib>Patelmo, Matteo</creatorcontrib><creatorcontrib>STMicroelectronics S.r.l</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Vajana, Bruno</au><au>Patelmo, Matteo</au><aucorp>STMicroelectronics S.r.l</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Mask programmed ROM inviolable by reverse engineering inspections and method of fabrication</title><date>2003-09-02</date><risdate>2003</risdate><abstract>The present invention relates in general to integrated circuits, and in particular, to a read only memory (ROM) device.
A read only memory (ROM) device includes a semiconductor substrate having a first type of conductivity, and a plurality of memory cells on the semiconductor substrate. Each memory cell includes first and second regions of a second conductivity type opposite the first conductivity type. A first dielectric layer is on the plurality of memory cells, and a plurality of first contacts extend through the first dielectric layer for contacting the first regions. A second dielectric layer is on the first dielectric layer and the plurality of first contacts. A plurality of second contacts extend through the second dielectric layer and overlie the corresponding second regions. The plurality of second contacts define interconnection contacts by further extending through the first dielectric layer for contacting the second regions for memory cells programmed in a conductive state, and false interconnection contacts by not extending through the first dielectric layer for contacting the second regions for memory cells programmed in a non-conductive state.</abstract><oa>free_for_read</oa></addata></record> |
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title | Mask programmed ROM inviolable by reverse engineering inspections and method of fabrication |
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