Memory access address comparison

The present invention relates to a memory system. A memory system comprises a memory array having a plurality of memory locations; a plurality of write ports for writing to the memory array; write protection circuitry for preventing more than one memory location from being addressed at the same time in a write operation, the write protection circuitry providing one write enable signal for each write port, the write enable signals being applied to the memory array; and circuitry for controlling the timing of the application of the write enable signals to the memory array, the circuitry for controlling the timing being upstream of the write protection circuitry.