System and method for interleaved execution of multiple independent threads

System and method for interleaved execution of multiple independent threads

The present invention is directed, in general, to processing systems and, more specifically, to a microprocessor that is capable of processing multiple independent threads of instruction code. There is disclosed an apparatus for loading instructions into the instruction execution pipeline of a pipel...

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Hauptverfasser: Nuechterlein, David W, Briggs, Willard S
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Sprache:eng
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creator Nuechterlein, David W
Briggs, Willard S
description The present invention is directed, in general, to processing systems and, more specifically, to a microprocessor that is capable of processing multiple independent threads of instruction code. There is disclosed an apparatus for loading instructions into the instruction execution pipeline of a pipelined processor. The apparatus for loading instructions comprises: 1) an instruction loading circuit that loads instructions from a first instruction thread into the instruction execution pipeline; and 2) a branch instruction detection circuit that detects a branch instruction in the first instruction thread. In response to the branch instruction detection, the instruction loading circuit stops loading instructions from the first instruction thread into the instruction execution pipeline and begins loading instructions from a second instruction thread into the instruction execution pipeline.
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There is disclosed an apparatus for loading instructions into the instruction execution pipeline of a pipelined processor. The apparatus for loading instructions comprises: 1) an instruction loading circuit that loads instructions from a first instruction thread into the instruction execution pipeline; and 2) a branch instruction detection circuit that detects a branch instruction in the first instruction thread. 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There is disclosed an apparatus for loading instructions into the instruction execution pipeline of a pipelined processor. The apparatus for loading instructions comprises: 1) an instruction loading circuit that loads instructions from a first instruction thread into the instruction execution pipeline; and 2) a branch instruction detection circuit that detects a branch instruction in the first instruction thread. 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There is disclosed an apparatus for loading instructions into the instruction execution pipeline of a pipelined processor. The apparatus for loading instructions comprises: 1) an instruction loading circuit that loads instructions from a first instruction thread into the instruction execution pipeline; and 2) a branch instruction detection circuit that detects a branch instruction in the first instruction thread. In response to the branch instruction detection, the instruction loading circuit stops loading instructions from the first instruction thread into the instruction execution pipeline and begins loading instructions from a second instruction thread into the instruction execution pipeline.</abstract><oa>free_for_read</oa></addata></record>
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title System and method for interleaved execution of multiple independent threads
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