System for adjusting clock frequency based upon amount of unread data stored in sequential memory when reading a new line of data within a field of data
1. Field of the Invention A method for adjusting timing of a secondary system with respect to a reference system is disclosed. The secondary and reference systems include a secondary synchronization signal and a reference synchronization signal, which are used to detect a phase difference between th...
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creator | Felts, III, Benjamin Edwin Shakeel, Asif Scott, Havard Lee |
description | 1. Field of the Invention
A method for adjusting timing of a secondary system with respect to a reference system is disclosed. The secondary and reference systems include a secondary synchronization signal and a reference synchronization signal, which are used to detect a phase difference between the secondary synchronization signal and the reference synchronization signal. A filtered phase error is generated from the detected phase difference. In addition, a frequency difference is detected between the secondary synchronization signal and the reference synchronization signal, and an instantaneous frequency difference and a filtered frequency error are generated from the detected frequency difference. The filtered phase error and the filtered frequency error are accumulated, and the timing of the secondary system is controlled in accordance with the accumulated filtered phase error, the accumulated filtered frequency error, and the instantaneous frequency difference. |
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A method for adjusting timing of a secondary system with respect to a reference system is disclosed. The secondary and reference systems include a secondary synchronization signal and a reference synchronization signal, which are used to detect a phase difference between the secondary synchronization signal and the reference synchronization signal. A filtered phase error is generated from the detected phase difference. In addition, a frequency difference is detected between the secondary synchronization signal and the reference synchronization signal, and an instantaneous frequency difference and a filtered frequency error are generated from the detected frequency difference. The filtered phase error and the filtered frequency error are accumulated, and the timing of the secondary system is controlled in accordance with the accumulated filtered phase error, the accumulated filtered frequency error, and the instantaneous frequency difference.</description><language>eng</language><creationdate>2003</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6581164$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,780,802,885,64039</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6581164$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Felts, III, Benjamin Edwin</creatorcontrib><creatorcontrib>Shakeel, Asif</creatorcontrib><creatorcontrib>Scott, Havard Lee</creatorcontrib><creatorcontrib>Conexant Systems, Inc</creatorcontrib><title>System for adjusting clock frequency based upon amount of unread data stored in sequential memory when reading a new line of data within a field of data</title><description>1. Field of the Invention
A method for adjusting timing of a secondary system with respect to a reference system is disclosed. The secondary and reference systems include a secondary synchronization signal and a reference synchronization signal, which are used to detect a phase difference between the secondary synchronization signal and the reference synchronization signal. A filtered phase error is generated from the detected phase difference. In addition, a frequency difference is detected between the secondary synchronization signal and the reference synchronization signal, and an instantaneous frequency difference and a filtered frequency error are generated from the detected frequency difference. The filtered phase error and the filtered frequency error are accumulated, and the timing of the secondary system is controlled in accordance with the accumulated filtered phase error, the accumulated filtered frequency error, and the instantaneous frequency difference.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2003</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNqNjT0KwkAUhNNYiHqHuYBgUIO9KPbayzP7Nq5u3sb9IeQmHtckaG81MHzfzDR7n7sQuYZ2HqQeKUQjFUrryie051diKTvcKLBCapyAapckwmkk8UwKiiIhROd7wgjC6ERDFjXXzndo7ywY0GGZINzCGuFhYnRbE--9SNCGrfrV82yiyQZefHOW4Xi47E_LFBqK_UO4Vp6GWBXbXZ4Xm_UfyAed-FJS</recordid><startdate>20030617</startdate><enddate>20030617</enddate><creator>Felts, III, Benjamin Edwin</creator><creator>Shakeel, Asif</creator><creator>Scott, Havard Lee</creator><scope>EFH</scope></search><sort><creationdate>20030617</creationdate><title>System for adjusting clock frequency based upon amount of unread data stored in sequential memory when reading a new line of data within a field of data</title><author>Felts, III, Benjamin Edwin ; Shakeel, Asif ; Scott, Havard Lee</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_065811643</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2003</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Felts, III, Benjamin Edwin</creatorcontrib><creatorcontrib>Shakeel, Asif</creatorcontrib><creatorcontrib>Scott, Havard Lee</creatorcontrib><creatorcontrib>Conexant Systems, Inc</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Felts, III, Benjamin Edwin</au><au>Shakeel, Asif</au><au>Scott, Havard Lee</au><aucorp>Conexant Systems, Inc</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>System for adjusting clock frequency based upon amount of unread data stored in sequential memory when reading a new line of data within a field of data</title><date>2003-06-17</date><risdate>2003</risdate><abstract>1. Field of the Invention
A method for adjusting timing of a secondary system with respect to a reference system is disclosed. The secondary and reference systems include a secondary synchronization signal and a reference synchronization signal, which are used to detect a phase difference between the secondary synchronization signal and the reference synchronization signal. A filtered phase error is generated from the detected phase difference. In addition, a frequency difference is detected between the secondary synchronization signal and the reference synchronization signal, and an instantaneous frequency difference and a filtered frequency error are generated from the detected frequency difference. The filtered phase error and the filtered frequency error are accumulated, and the timing of the secondary system is controlled in accordance with the accumulated filtered phase error, the accumulated filtered frequency error, and the instantaneous frequency difference.</abstract><oa>free_for_read</oa></addata></record> |
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title | System for adjusting clock frequency based upon amount of unread data stored in sequential memory when reading a new line of data within a field of data |
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