Process line for underfilling a controlled collapse
1. Field of the Invention A high throughput process line and method for underfilling an integrated circuit that is mounted to a substrate. The process line includes a first dispensing station that dispenses a first underfill material onto the substrate and an oven which moves the substrate while the...
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| creator | Cook, Duane Ramalingam, Suresh |
| description | 1. Field of the Invention
A high throughput process line and method for underfilling an integrated circuit that is mounted to a substrate. The process line includes a first dispensing station that dispenses a first underfill material onto the substrate and an oven which moves the substrate while the underfill material flows between the integrated circuit and the substrate. The process line removes flow time (wicking time) as the bottleneck for achieving high throughput. |
| format | Patent |
| fullrecord | <record><control><sourceid>uspatents_EFH</sourceid><recordid>TN_cdi_uspatents_grants_06528345</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>06528345</sourcerecordid><originalsourceid>FETCH-uspatents_grants_065283453</originalsourceid><addsrcrecordid>eNrjZDAOKMpPTi0uVsjJzEtVSMsvUijNS0ktSsvMAQqkKyQqJOfnlRTl5-SkpgCZOTmJBcWpPAysaYk5xam8UJqbQcHNNcTZQ7e0uCCxJDWvpDg-vSgRRBmYmRpZGJuYGhOhBADiOi2F</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Process line for underfilling a controlled collapse</title><source>USPTO Issued Patents</source><creator>Cook, Duane ; Ramalingam, Suresh</creator><creatorcontrib>Cook, Duane ; Ramalingam, Suresh ; Intel Corporation</creatorcontrib><description>1. Field of the Invention
A high throughput process line and method for underfilling an integrated circuit that is mounted to a substrate. The process line includes a first dispensing station that dispenses a first underfill material onto the substrate and an oven which moves the substrate while the underfill material flows between the integrated circuit and the substrate. The process line removes flow time (wicking time) as the bottleneck for achieving high throughput.</description><language>eng</language><creationdate>2003</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6528345$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,776,798,881,64012</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6528345$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Cook, Duane</creatorcontrib><creatorcontrib>Ramalingam, Suresh</creatorcontrib><creatorcontrib>Intel Corporation</creatorcontrib><title>Process line for underfilling a controlled collapse</title><description>1. Field of the Invention
A high throughput process line and method for underfilling an integrated circuit that is mounted to a substrate. The process line includes a first dispensing station that dispenses a first underfill material onto the substrate and an oven which moves the substrate while the underfill material flows between the integrated circuit and the substrate. The process line removes flow time (wicking time) as the bottleneck for achieving high throughput.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2003</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNrjZDAOKMpPTi0uVsjJzEtVSMsvUijNS0ktSsvMAQqkKyQqJOfnlRTl5-SkpgCZOTmJBcWpPAysaYk5xam8UJqbQcHNNcTZQ7e0uCCxJDWvpDg-vSgRRBmYmRpZGJuYGhOhBADiOi2F</recordid><startdate>20030304</startdate><enddate>20030304</enddate><creator>Cook, Duane</creator><creator>Ramalingam, Suresh</creator><scope>EFH</scope></search><sort><creationdate>20030304</creationdate><title>Process line for underfilling a controlled collapse</title><author>Cook, Duane ; Ramalingam, Suresh</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_065283453</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2003</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Cook, Duane</creatorcontrib><creatorcontrib>Ramalingam, Suresh</creatorcontrib><creatorcontrib>Intel Corporation</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Cook, Duane</au><au>Ramalingam, Suresh</au><aucorp>Intel Corporation</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Process line for underfilling a controlled collapse</title><date>2003-03-04</date><risdate>2003</risdate><abstract>1. Field of the Invention
A high throughput process line and method for underfilling an integrated circuit that is mounted to a substrate. The process line includes a first dispensing station that dispenses a first underfill material onto the substrate and an oven which moves the substrate while the underfill material flows between the integrated circuit and the substrate. The process line removes flow time (wicking time) as the bottleneck for achieving high throughput.</abstract><oa>free_for_read</oa></addata></record> |
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| source | USPTO Issued Patents |
| title | Process line for underfilling a controlled collapse |
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