Method and apparatus for dynamic power control of a low power processor
1. Field Briefly, in accordance with one embodiment of the invention, a system includes: a processor, a voltage regulator, and a memory. The voltage regulator is coupled to the processor to adjust the operating voltage of the processor. The memory is coupled to the processor by a memory bus. The mem...
Gespeichert in:
| Hauptverfasser: | , , , |
|---|---|
| Format: | Patent |
| Sprache: | eng |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | Clark, Lawrence T McDaniel, Bart Heeb, Jay Adelmeyer, Tom J |
| description | 1. Field
Briefly, in accordance with one embodiment of the invention, a system includes: a processor, a voltage regulator, and a memory. The voltage regulator is coupled to the processor to adjust the operating voltage of the processor. The memory is coupled to the processor by a memory bus. The memory has stored on it processor instructions that, when executed by the processor, result in modification of the operating frequency of the processor and result in adjustment of the operating voltage of the processor, based, at least in part, on dynamic changes in the processing load of the processor. |
| format | Patent |
| fullrecord | <record><control><sourceid>uspatents_EFH</sourceid><recordid>TN_cdi_uspatents_grants_06519707</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>06519707</sourcerecordid><originalsourceid>FETCH-uspatents_grants_065197073</originalsourceid><addsrcrecordid>eNrjZHD3TS3JyE9RSMwD4oKCxKLEktJihbT8IoWUyrzE3MxkhYL88tQiheT8vJKi_ByF_DSFRIWc_HKocEFRfnJqcXF-EQ8Da1piTnEqL5TmZlBwcw1x9tAtLS5ILEnNKymOTy9KBFEGZqaGluYG5sZEKAEAIvw01g</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method and apparatus for dynamic power control of a low power processor</title><source>USPTO Issued Patents</source><creator>Clark, Lawrence T ; McDaniel, Bart ; Heeb, Jay ; Adelmeyer, Tom J</creator><creatorcontrib>Clark, Lawrence T ; McDaniel, Bart ; Heeb, Jay ; Adelmeyer, Tom J ; Intel Corporation</creatorcontrib><description>1. Field
Briefly, in accordance with one embodiment of the invention, a system includes: a processor, a voltage regulator, and a memory. The voltage regulator is coupled to the processor to adjust the operating voltage of the processor. The memory is coupled to the processor by a memory bus. The memory has stored on it processor instructions that, when executed by the processor, result in modification of the operating frequency of the processor and result in adjustment of the operating voltage of the processor, based, at least in part, on dynamic changes in the processing load of the processor.</description><language>eng</language><creationdate>2003</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6519707$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,776,798,881,64012</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6519707$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Clark, Lawrence T</creatorcontrib><creatorcontrib>McDaniel, Bart</creatorcontrib><creatorcontrib>Heeb, Jay</creatorcontrib><creatorcontrib>Adelmeyer, Tom J</creatorcontrib><creatorcontrib>Intel Corporation</creatorcontrib><title>Method and apparatus for dynamic power control of a low power processor</title><description>1. Field
Briefly, in accordance with one embodiment of the invention, a system includes: a processor, a voltage regulator, and a memory. The voltage regulator is coupled to the processor to adjust the operating voltage of the processor. The memory is coupled to the processor by a memory bus. The memory has stored on it processor instructions that, when executed by the processor, result in modification of the operating frequency of the processor and result in adjustment of the operating voltage of the processor, based, at least in part, on dynamic changes in the processing load of the processor.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2003</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNrjZHD3TS3JyE9RSMwD4oKCxKLEktJihbT8IoWUyrzE3MxkhYL88tQiheT8vJKi_ByF_DSFRIWc_HKocEFRfnJqcXF-EQ8Da1piTnEqL5TmZlBwcw1x9tAtLS5ILEnNKymOTy9KBFEGZqaGluYG5sZEKAEAIvw01g</recordid><startdate>20030211</startdate><enddate>20030211</enddate><creator>Clark, Lawrence T</creator><creator>McDaniel, Bart</creator><creator>Heeb, Jay</creator><creator>Adelmeyer, Tom J</creator><scope>EFH</scope></search><sort><creationdate>20030211</creationdate><title>Method and apparatus for dynamic power control of a low power processor</title><author>Clark, Lawrence T ; McDaniel, Bart ; Heeb, Jay ; Adelmeyer, Tom J</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_065197073</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2003</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Clark, Lawrence T</creatorcontrib><creatorcontrib>McDaniel, Bart</creatorcontrib><creatorcontrib>Heeb, Jay</creatorcontrib><creatorcontrib>Adelmeyer, Tom J</creatorcontrib><creatorcontrib>Intel Corporation</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Clark, Lawrence T</au><au>McDaniel, Bart</au><au>Heeb, Jay</au><au>Adelmeyer, Tom J</au><aucorp>Intel Corporation</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method and apparatus for dynamic power control of a low power processor</title><date>2003-02-11</date><risdate>2003</risdate><abstract>1. Field
Briefly, in accordance with one embodiment of the invention, a system includes: a processor, a voltage regulator, and a memory. The voltage regulator is coupled to the processor to adjust the operating voltage of the processor. The memory is coupled to the processor by a memory bus. The memory has stored on it processor instructions that, when executed by the processor, result in modification of the operating frequency of the processor and result in adjustment of the operating voltage of the processor, based, at least in part, on dynamic changes in the processing load of the processor.</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng |
| recordid | cdi_uspatents_grants_06519707 |
| source | USPTO Issued Patents |
| title | Method and apparatus for dynamic power control of a low power processor |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-30T20%3A44%3A00IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-uspatents_EFH&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Clark,%20Lawrence%20T&rft.aucorp=Intel%20Corporation&rft.date=2003-02-11&rft_id=info:doi/&rft_dat=%3Cuspatents_EFH%3E06519707%3C/uspatents_EFH%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |