Method and structure of column interconnect
1. Field of the Invention A method and structure for a semiconductor chip includes a plurality of layers of interconnect metallurgy, at least one layer of deformable dielectric material over the interconnect metallurgy, at least one input/output bonding pad, and a support structure that includes a s...
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creator | Ellis-Monaghan, John J Feeney, Paul M Geffken, Robert M Landis, Howard S Previti-Kelly, Rosemary A Bergman Reuter, Bette L Rutten, Matthew J Stamper, Anthony K Yankee, Sally J |
description | 1. Field of the Invention
A method and structure for a semiconductor chip includes a plurality of layers of interconnect metallurgy, at least one layer of deformable dielectric material over the interconnect metallurgy, at least one input/output bonding pad, and a support structure that includes a substantially rigid dielectric in a supporting relationship to the pad that avoids crushing the deformable dielectric material. |
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fullrecord | <record><control><sourceid>uspatents_EFH</sourceid><recordid>TN_cdi_uspatents_grants_06495917</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>06495917</sourcerecordid><originalsourceid>FETCH-uspatents_grants_064959173</originalsourceid><addsrcrecordid>eNrjZND2TS3JyE9RSMxLUSguKSpNLiktSlXIT1NIzs8pzc1TyMwrSS1Kzs_LS00u4WFgTUvMKU7lhdLcDApuriHOHrqlxQWJJal5JcXx6UWJIMrAzMTS1NLQ3JgIJQBTiSqm</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method and structure of column interconnect</title><source>USPTO Issued Patents</source><creator>Ellis-Monaghan, John J ; Feeney, Paul M ; Geffken, Robert M ; Landis, Howard S ; Previti-Kelly, Rosemary A ; Bergman Reuter, Bette L ; Rutten, Matthew J ; Stamper, Anthony K ; Yankee, Sally J</creator><creatorcontrib>Ellis-Monaghan, John J ; Feeney, Paul M ; Geffken, Robert M ; Landis, Howard S ; Previti-Kelly, Rosemary A ; Bergman Reuter, Bette L ; Rutten, Matthew J ; Stamper, Anthony K ; Yankee, Sally J ; International Business Machines Corporation</creatorcontrib><description>1. Field of the Invention
A method and structure for a semiconductor chip includes a plurality of layers of interconnect metallurgy, at least one layer of deformable dielectric material over the interconnect metallurgy, at least one input/output bonding pad, and a support structure that includes a substantially rigid dielectric in a supporting relationship to the pad that avoids crushing the deformable dielectric material.</description><language>eng</language><creationdate>2002</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6495917$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,780,802,885,64039</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6495917$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Ellis-Monaghan, John J</creatorcontrib><creatorcontrib>Feeney, Paul M</creatorcontrib><creatorcontrib>Geffken, Robert M</creatorcontrib><creatorcontrib>Landis, Howard S</creatorcontrib><creatorcontrib>Previti-Kelly, Rosemary A</creatorcontrib><creatorcontrib>Bergman Reuter, Bette L</creatorcontrib><creatorcontrib>Rutten, Matthew J</creatorcontrib><creatorcontrib>Stamper, Anthony K</creatorcontrib><creatorcontrib>Yankee, Sally J</creatorcontrib><creatorcontrib>International Business Machines Corporation</creatorcontrib><title>Method and structure of column interconnect</title><description>1. Field of the Invention
A method and structure for a semiconductor chip includes a plurality of layers of interconnect metallurgy, at least one layer of deformable dielectric material over the interconnect metallurgy, at least one input/output bonding pad, and a support structure that includes a substantially rigid dielectric in a supporting relationship to the pad that avoids crushing the deformable dielectric material.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2002</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNrjZND2TS3JyE9RSMxLUSguKSpNLiktSlXIT1NIzs8pzc1TyMwrSS1Kzs_LS00u4WFgTUvMKU7lhdLcDApuriHOHrqlxQWJJal5JcXx6UWJIMrAzMTS1NLQ3JgIJQBTiSqm</recordid><startdate>20021217</startdate><enddate>20021217</enddate><creator>Ellis-Monaghan, John J</creator><creator>Feeney, Paul M</creator><creator>Geffken, Robert M</creator><creator>Landis, Howard S</creator><creator>Previti-Kelly, Rosemary A</creator><creator>Bergman Reuter, Bette L</creator><creator>Rutten, Matthew J</creator><creator>Stamper, Anthony K</creator><creator>Yankee, Sally J</creator><scope>EFH</scope></search><sort><creationdate>20021217</creationdate><title>Method and structure of column interconnect</title><author>Ellis-Monaghan, John J ; Feeney, Paul M ; Geffken, Robert M ; Landis, Howard S ; Previti-Kelly, Rosemary A ; Bergman Reuter, Bette L ; Rutten, Matthew J ; Stamper, Anthony K ; Yankee, Sally J</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_064959173</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2002</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Ellis-Monaghan, John J</creatorcontrib><creatorcontrib>Feeney, Paul M</creatorcontrib><creatorcontrib>Geffken, Robert M</creatorcontrib><creatorcontrib>Landis, Howard S</creatorcontrib><creatorcontrib>Previti-Kelly, Rosemary A</creatorcontrib><creatorcontrib>Bergman Reuter, Bette L</creatorcontrib><creatorcontrib>Rutten, Matthew J</creatorcontrib><creatorcontrib>Stamper, Anthony K</creatorcontrib><creatorcontrib>Yankee, Sally J</creatorcontrib><creatorcontrib>International Business Machines Corporation</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Ellis-Monaghan, John J</au><au>Feeney, Paul M</au><au>Geffken, Robert M</au><au>Landis, Howard S</au><au>Previti-Kelly, Rosemary A</au><au>Bergman Reuter, Bette L</au><au>Rutten, Matthew J</au><au>Stamper, Anthony K</au><au>Yankee, Sally J</au><aucorp>International Business Machines Corporation</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method and structure of column interconnect</title><date>2002-12-17</date><risdate>2002</risdate><abstract>1. Field of the Invention
A method and structure for a semiconductor chip includes a plurality of layers of interconnect metallurgy, at least one layer of deformable dielectric material over the interconnect metallurgy, at least one input/output bonding pad, and a support structure that includes a substantially rigid dielectric in a supporting relationship to the pad that avoids crushing the deformable dielectric material.</abstract><oa>free_for_read</oa></addata></record> |
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title | Method and structure of column interconnect |
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