Method for eliminating crack damage induced by delaminating gate conductor interfaces in integrated circuits

This invention generally relates to methods of manufacturing integrated circuits ("IC"), memory circuits or memory chips. More particularly, this invention relates to a method for manufacturing ICs to manage crack damage and propagation especially where the crack damage is induced by the delamination of the gate conductor surface interfaces during the IC wafer dicing process. A method for manufacturing integrated circuits ("IC") on wafers to manage crack damage in the ICs such that crack propagation into the IC active array is reduced or eliminated. The method provides for a defined separation or divide of the IC gate conductor from the IC crack stop or IC edge. The method is especially useful in managing crack damage induced through the delamination of one or more of the gate conductor surface interfaces as a result of the IC wafer dicing process. Circuits or chips manufactured according to the methods disclosed are also taught.