Method and system for testing an integrated circuit

Method and system for testing an integrated circuit

1. Technical Field The foregoing objects are achieved as is now described. A method and system for testing an integrated circuit are provided. A test substrate is provided which is manufactured by the same particular production technology for which the complex integrated circuit is designed. A patte...

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Hauptverfasser: Bailey, Roger Ned, Floyd, Michael Stephen, McCredie, Bradley, Reick, Kevin Franklin, Stigdon, Hugh Rodney, Vargus, Jennifer Lane
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Sprache:eng
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creator Bailey, Roger Ned
Floyd, Michael Stephen
McCredie, Bradley
Reick, Kevin Franklin
Stigdon, Hugh Rodney
Vargus, Jennifer Lane
description 1. Technical Field The foregoing objects are achieved as is now described. A method and system for testing an integrated circuit are provided. A test substrate is provided which is manufactured by the same particular production technology for which the complex integrated circuit is designed. A pattern generator for generating test data and a result checker for comparing output data are embedded on the test substrate. Isolated portions of circuitry of the integrated circuit are selectively embedded onto the test substrate. The isolated portions of circuitry are subjected to testing by applying test data from the pattern generator to the isolated portions of circuitry. Errors in the isolated portions of circuitry are detected with the result checker by comparing data output from the isolated portions of circuitry with predetermined expected data, such that the integrated circuit is tested by susets, independently of testing the integrated circuit in its entirety.
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fullrecord <record><control><sourceid>uspatents_EFH</sourceid><recordid>TN_cdi_uspatents_grants_06438722</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>06438722</sourcerecordid><originalsourceid>FETCH-uspatents_grants_064387223</originalsourceid><addsrcrecordid>eNrjZDD2TS3JyE9RSMxLUSiuLC5JzVVIyy9SKEktLsnMSwcKK2TmlaSmFyWWpKYoJGcWJZdmlvAwsKYl5hSn8kJpbgYFN9cQZw_d0uICoLq8kuJ4oAYQZWBmYmxhbmRkTIQSAMkGLU8</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method and system for testing an integrated circuit</title><source>USPTO Issued Patents</source><creator>Bailey, Roger Ned ; Floyd, Michael Stephen ; McCredie, Bradley ; Reick, Kevin Franklin ; Stigdon, Hugh Rodney ; Vargus, Jennifer Lane</creator><creatorcontrib>Bailey, Roger Ned ; Floyd, Michael Stephen ; McCredie, Bradley ; Reick, Kevin Franklin ; Stigdon, Hugh Rodney ; Vargus, Jennifer Lane ; International Business Machines Corporation</creatorcontrib><description>1. Technical Field The foregoing objects are achieved as is now described. A method and system for testing an integrated circuit are provided. A test substrate is provided which is manufactured by the same particular production technology for which the complex integrated circuit is designed. A pattern generator for generating test data and a result checker for comparing output data are embedded on the test substrate. Isolated portions of circuitry of the integrated circuit are selectively embedded onto the test substrate. The isolated portions of circuitry are subjected to testing by applying test data from the pattern generator to the isolated portions of circuitry. Errors in the isolated portions of circuitry are detected with the result checker by comparing data output from the isolated portions of circuitry with predetermined expected data, such that the integrated circuit is tested by susets, independently of testing the integrated circuit in its entirety.</description><language>eng</language><creationdate>2002</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6438722$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,780,802,885,64037</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6438722$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Bailey, Roger Ned</creatorcontrib><creatorcontrib>Floyd, Michael Stephen</creatorcontrib><creatorcontrib>McCredie, Bradley</creatorcontrib><creatorcontrib>Reick, Kevin Franklin</creatorcontrib><creatorcontrib>Stigdon, Hugh Rodney</creatorcontrib><creatorcontrib>Vargus, Jennifer Lane</creatorcontrib><creatorcontrib>International Business Machines Corporation</creatorcontrib><title>Method and system for testing an integrated circuit</title><description>1. Technical Field The foregoing objects are achieved as is now described. A method and system for testing an integrated circuit are provided. A test substrate is provided which is manufactured by the same particular production technology for which the complex integrated circuit is designed. A pattern generator for generating test data and a result checker for comparing output data are embedded on the test substrate. Isolated portions of circuitry of the integrated circuit are selectively embedded onto the test substrate. The isolated portions of circuitry are subjected to testing by applying test data from the pattern generator to the isolated portions of circuitry. Errors in the isolated portions of circuitry are detected with the result checker by comparing data output from the isolated portions of circuitry with predetermined expected data, such that the integrated circuit is tested by susets, independently of testing the integrated circuit in its entirety.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2002</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNrjZDD2TS3JyE9RSMxLUSiuLC5JzVVIyy9SKEktLsnMSwcKK2TmlaSmFyWWpKYoJGcWJZdmlvAwsKYl5hSn8kJpbgYFN9cQZw_d0uICoLq8kuJ4oAYQZWBmYmxhbmRkTIQSAMkGLU8</recordid><startdate>20020820</startdate><enddate>20020820</enddate><creator>Bailey, Roger Ned</creator><creator>Floyd, Michael Stephen</creator><creator>McCredie, Bradley</creator><creator>Reick, Kevin Franklin</creator><creator>Stigdon, Hugh Rodney</creator><creator>Vargus, Jennifer Lane</creator><scope>EFH</scope></search><sort><creationdate>20020820</creationdate><title>Method and system for testing an integrated circuit</title><author>Bailey, Roger Ned ; Floyd, Michael Stephen ; McCredie, Bradley ; Reick, Kevin Franklin ; Stigdon, Hugh Rodney ; Vargus, Jennifer Lane</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_064387223</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2002</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Bailey, Roger Ned</creatorcontrib><creatorcontrib>Floyd, Michael Stephen</creatorcontrib><creatorcontrib>McCredie, Bradley</creatorcontrib><creatorcontrib>Reick, Kevin Franklin</creatorcontrib><creatorcontrib>Stigdon, Hugh Rodney</creatorcontrib><creatorcontrib>Vargus, Jennifer Lane</creatorcontrib><creatorcontrib>International Business Machines Corporation</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Bailey, Roger Ned</au><au>Floyd, Michael Stephen</au><au>McCredie, Bradley</au><au>Reick, Kevin Franklin</au><au>Stigdon, Hugh Rodney</au><au>Vargus, Jennifer Lane</au><aucorp>International Business Machines Corporation</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method and system for testing an integrated circuit</title><date>2002-08-20</date><risdate>2002</risdate><abstract>1. Technical Field The foregoing objects are achieved as is now described. A method and system for testing an integrated circuit are provided. A test substrate is provided which is manufactured by the same particular production technology for which the complex integrated circuit is designed. A pattern generator for generating test data and a result checker for comparing output data are embedded on the test substrate. Isolated portions of circuitry of the integrated circuit are selectively embedded onto the test substrate. The isolated portions of circuitry are subjected to testing by applying test data from the pattern generator to the isolated portions of circuitry. Errors in the isolated portions of circuitry are detected with the result checker by comparing data output from the isolated portions of circuitry with predetermined expected data, such that the integrated circuit is tested by susets, independently of testing the integrated circuit in its entirety.</abstract><oa>free_for_read</oa></addata></record>
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title Method and system for testing an integrated circuit
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-10T02%3A35%3A21IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-uspatents_EFH&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Bailey,%20Roger%20Ned&rft.aucorp=International%20Business%20Machines%20Corporation&rft.date=2002-08-20&rft_id=info:doi/&rft_dat=%3Cuspatents_EFH%3E06438722%3C/uspatents_EFH%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true