Detection of data hazards between instructions by decoding register indentifiers in each stage of processing system pipeline and comparing asserted bits in the decoded register indentifiers

1. Field of the Invention A computer system utilizing a processing system capable of efficiently comparing register identifiers to detect data hazards between instructions of a computer program is used to execute the computer program. The processing system utilizes at least one pipeline, a first decoder, a second decoder, and comparison logic. The pipeline receives and simultaneously processes instructions of a computer program. The first and second decoders are coupled to the pipeline and decode register identifiers associated with instructions being processed by the pipeline. The comparison logic is interfaced with the first and second decoders and respectively compares the decoded register identifiers produced by the first and second decoders to other decoded register identifiers.