Semiconductor device having high breakdown voltage and method for manufacturing the device

Semiconductor device having high breakdown voltage and method for manufacturing the device

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. filed Mar. 11, 1999, the entire contents of which are incorporated herein by reference. A power device has its main junction formed in a central portion of an N-type substrate. A P-type l...

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Hauptverfasser: Tsuchitani, Masanobu, Satou, Shingo
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creator Tsuchitani, Masanobu
Satou, Shingo
description This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. filed Mar. 11, 1999, the entire contents of which are incorporated herein by reference. A power device has its main junction formed in a central portion of an N-type substrate. A P-type layer is formed in a peripheral surface portion of the substrate. A P-type RESURF layer of a lower impurity concentration than the P-type layer is formed outside and in contact with the P-type layer. An N-channel stopper layer is formed in an edge surface portion of the substrate. The channel stopper layer is separated from the RESURF layer by a predetermined distance. A recess is formed in that surface portion of the substrate between the P-type layer and the channel stopper layer, which includes a surface portion of the RESURF layer. A semiconductive film is formed in the recess. The RESURF layer has an impurity concentration of about 10-10atoms/cmwhere it contacts the semiconductive film.
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fullrecord <record><control><sourceid>uspatents_EFH</sourceid><recordid>TN_cdi_uspatents_grants_06429501</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>06429501</sourcerecordid><originalsourceid>FETCH-uspatents_grants_064295013</originalsourceid><addsrcrecordid>eNqNjDsKAjEQQNNYiHqHuYCwfsFaFHutbGRMJh_cTCSZxOvrwh7A6jXvvam6XykGndhULSmDoRY0gccW2IEPzsMzE75M-jC01As6AmQDkcQnA_bXRORqUUvNQyOexstcTSz2hRYjZwrOp9vxsqzljUIs5eEyDuj22_Vh1602fyhfEEI8QA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Semiconductor device having high breakdown voltage and method for manufacturing the device</title><source>USPTO Issued Patents</source><creator>Tsuchitani, Masanobu ; Satou, Shingo</creator><creatorcontrib>Tsuchitani, Masanobu ; Satou, Shingo ; Kabushiki Kaisha Toshiba</creatorcontrib><description>This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. filed Mar. 11, 1999, the entire contents of which are incorporated herein by reference. A power device has its main junction formed in a central portion of an N-type substrate. A P-type layer is formed in a peripheral surface portion of the substrate. A P-type RESURF layer of a lower impurity concentration than the P-type layer is formed outside and in contact with the P-type layer. An N-channel stopper layer is formed in an edge surface portion of the substrate. The channel stopper layer is separated from the RESURF layer by a predetermined distance. A recess is formed in that surface portion of the substrate between the P-type layer and the channel stopper layer, which includes a surface portion of the RESURF layer. A semiconductive film is formed in the recess. The RESURF layer has an impurity concentration of about 10-10atoms/cmwhere it contacts the semiconductive film.</description><language>eng</language><creationdate>2002</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6429501$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,780,802,885,64039</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6429501$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Tsuchitani, Masanobu</creatorcontrib><creatorcontrib>Satou, Shingo</creatorcontrib><creatorcontrib>Kabushiki Kaisha Toshiba</creatorcontrib><title>Semiconductor device having high breakdown voltage and method for manufacturing the device</title><description>This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. filed Mar. 11, 1999, the entire contents of which are incorporated herein by reference. A power device has its main junction formed in a central portion of an N-type substrate. A P-type layer is formed in a peripheral surface portion of the substrate. A P-type RESURF layer of a lower impurity concentration than the P-type layer is formed outside and in contact with the P-type layer. An N-channel stopper layer is formed in an edge surface portion of the substrate. The channel stopper layer is separated from the RESURF layer by a predetermined distance. A recess is formed in that surface portion of the substrate between the P-type layer and the channel stopper layer, which includes a surface portion of the RESURF layer. A semiconductive film is formed in the recess. The RESURF layer has an impurity concentration of about 10-10atoms/cmwhere it contacts the semiconductive film.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2002</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNqNjDsKAjEQQNNYiHqHuYCwfsFaFHutbGRMJh_cTCSZxOvrwh7A6jXvvam6XykGndhULSmDoRY0gccW2IEPzsMzE75M-jC01As6AmQDkcQnA_bXRORqUUvNQyOexstcTSz2hRYjZwrOp9vxsqzljUIs5eEyDuj22_Vh1602fyhfEEI8QA</recordid><startdate>20020806</startdate><enddate>20020806</enddate><creator>Tsuchitani, Masanobu</creator><creator>Satou, Shingo</creator><scope>EFH</scope></search><sort><creationdate>20020806</creationdate><title>Semiconductor device having high breakdown voltage and method for manufacturing the device</title><author>Tsuchitani, Masanobu ; Satou, Shingo</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_064295013</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2002</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Tsuchitani, Masanobu</creatorcontrib><creatorcontrib>Satou, Shingo</creatorcontrib><creatorcontrib>Kabushiki Kaisha Toshiba</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Tsuchitani, Masanobu</au><au>Satou, Shingo</au><aucorp>Kabushiki Kaisha Toshiba</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Semiconductor device having high breakdown voltage and method for manufacturing the device</title><date>2002-08-06</date><risdate>2002</risdate><abstract>This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. filed Mar. 11, 1999, the entire contents of which are incorporated herein by reference. A power device has its main junction formed in a central portion of an N-type substrate. A P-type layer is formed in a peripheral surface portion of the substrate. A P-type RESURF layer of a lower impurity concentration than the P-type layer is formed outside and in contact with the P-type layer. An N-channel stopper layer is formed in an edge surface portion of the substrate. The channel stopper layer is separated from the RESURF layer by a predetermined distance. A recess is formed in that surface portion of the substrate between the P-type layer and the channel stopper layer, which includes a surface portion of the RESURF layer. A semiconductive film is formed in the recess. The RESURF layer has an impurity concentration of about 10-10atoms/cmwhere it contacts the semiconductive film.</abstract><oa>free_for_read</oa></addata></record>
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title Semiconductor device having high breakdown voltage and method for manufacturing the device
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-21T09%3A58%3A28IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-uspatents_EFH&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Tsuchitani,%20Masanobu&rft.aucorp=Kabushiki%20Kaisha%20Toshiba&rft.date=2002-08-06&rft_id=info:doi/&rft_dat=%3Cuspatents_EFH%3E06429501%3C/uspatents_EFH%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true