Dual mask process for semiconductor devices

This invention relates to the manufacture of integrated circuit devices on a semiconductor substrate. In particular, the present invention relates to a fabrication process for making a logic device with embedded memory where the memory and logic FETs require only one additional DUV mask to create separate hard masks for the gate in DRAM arrays, DRAM support, and logic devices. A method for fabricating a dual gate structure, comprising providing a semiconductor substrate having a first device area and a second device area covered by a gate oxide layer and a polysilicon layer, forming a first hard mask over the polysilicon layer, said first hard mask being a material that is resistant to a first etching, but susceptible to a second etching forming a second hard mask over the first hard mask and the polysilicon layer, said second hard mask being a material that is resistant to a second etching, but susceptible to a first etching, patterning and etching said second hard mask with a first etch to form a gate pattern on a first device area, and patterning and etching said first hard mask with a second etch to transfer gate patterns on the first and second device areas.