Pulse width modulation signal generator

1. Field of the Invention A PWM signal generator allowing a desired combination of cycle and duty to be reliably generated from cycle and duty set values received from a CPU is disclosed. A cycle comparator compares a counted value of a timer to a cycle set value and a duty comparator compares the counted value to a duty set value. A PWM output circuit outputs a PWM signal that is set and reset depending on a combination of a cycle coincidence signal and a duty coincidence signal generated from the cycle and duty comparators, respectively. A transfer controller controls transfers timing of cycle and duty set values while monitoring the cycle coincidence signal and the write timing of the cycle and duty set values.