Non-volatile latch
1. Field of the Invention A non-volatile latch comprises first and second read/write bias nodes and first and second a complementary output nodes. First and second first conductivity type MOS transistors have sources coupled to a first voltage potential. A drain of the first MOS transistor is couple...
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| creator | Caywood, John |
| description | 1. Field of the Invention
A non-volatile latch comprises first and second read/write bias nodes and first and second a complementary output nodes. First and second first conductivity type MOS transistors have sources coupled to a first voltage potential. A drain of the first MOS transistor is coupled to the first complementary output node and a drain of the second MOS transistor is coupled to the second complementary output node. Each of the first and second MOS transistors have a gate cross coupled to the drain of the other one of the first and second MOS transistor. A source of a third MOS transistor is coupled to the first read/write bias node and a source of a fourth MOS transistor is coupled to the second read/write bias node. A drain of the third MOS transistor is coupled to the first complementary output node and a drain of the fourth MOS transistor is coupled to the second complementary output node. Each of the third and fourth MOS transistors have a gate cross coupled to the source of the other one of the third and fourth MOS transistors. |
| format | Patent |
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A non-volatile latch comprises first and second read/write bias nodes and first and second a complementary output nodes. First and second first conductivity type MOS transistors have sources coupled to a first voltage potential. A drain of the first MOS transistor is coupled to the first complementary output node and a drain of the second MOS transistor is coupled to the second complementary output node. Each of the first and second MOS transistors have a gate cross coupled to the drain of the other one of the first and second MOS transistor. A source of a third MOS transistor is coupled to the first read/write bias node and a source of a fourth MOS transistor is coupled to the second read/write bias node. A drain of the third MOS transistor is coupled to the first complementary output node and a drain of the fourth MOS transistor is coupled to the second complementary output node. Each of the third and fourth MOS transistors have a gate cross coupled to the source of the other one of the third and fourth MOS transistors.</description><language>eng</language><creationdate>2002</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6411545$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,776,798,881,64012</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6411545$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Caywood, John</creatorcontrib><creatorcontrib>John Millard and Pamela Ann Caywood 1989 Revokable Living Trust</creatorcontrib><title>Non-volatile latch</title><description>1. Field of the Invention
A non-volatile latch comprises first and second read/write bias nodes and first and second a complementary output nodes. First and second first conductivity type MOS transistors have sources coupled to a first voltage potential. A drain of the first MOS transistor is coupled to the first complementary output node and a drain of the second MOS transistor is coupled to the second complementary output node. Each of the first and second MOS transistors have a gate cross coupled to the drain of the other one of the first and second MOS transistor. A source of a third MOS transistor is coupled to the first read/write bias node and a source of a fourth MOS transistor is coupled to the second read/write bias node. A drain of the third MOS transistor is coupled to the first complementary output node and a drain of the fourth MOS transistor is coupled to the second complementary output node. Each of the third and fourth MOS transistors have a gate cross coupled to the source of the other one of the third and fourth MOS transistors.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2002</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNrjZBDyy8_TLcvPSSzJzElVAFLJGTwMrGmJOcWpvFCam0HBzTXE2UO3tLggsSQ1r6Q4Pr0oEUQZmJkYGpqamBoToQQA28cgvw</recordid><startdate>20020625</startdate><enddate>20020625</enddate><creator>Caywood, John</creator><scope>EFH</scope></search><sort><creationdate>20020625</creationdate><title>Non-volatile latch</title><author>Caywood, John</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_064115453</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2002</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Caywood, John</creatorcontrib><creatorcontrib>John Millard and Pamela Ann Caywood 1989 Revokable Living Trust</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Caywood, John</au><aucorp>John Millard and Pamela Ann Caywood 1989 Revokable Living Trust</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Non-volatile latch</title><date>2002-06-25</date><risdate>2002</risdate><abstract>1. Field of the Invention
A non-volatile latch comprises first and second read/write bias nodes and first and second a complementary output nodes. First and second first conductivity type MOS transistors have sources coupled to a first voltage potential. A drain of the first MOS transistor is coupled to the first complementary output node and a drain of the second MOS transistor is coupled to the second complementary output node. Each of the first and second MOS transistors have a gate cross coupled to the drain of the other one of the first and second MOS transistor. A source of a third MOS transistor is coupled to the first read/write bias node and a source of a fourth MOS transistor is coupled to the second read/write bias node. A drain of the third MOS transistor is coupled to the first complementary output node and a drain of the fourth MOS transistor is coupled to the second complementary output node. Each of the third and fourth MOS transistors have a gate cross coupled to the source of the other one of the third and fourth MOS transistors.</abstract><oa>free_for_read</oa></addata></record> |
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| title | Non-volatile latch |
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