Scheduler for avoiding bank conflicts in issuing concurrent requests to main memory

Main memory ( ) for a conventional computer is normally implemented by one or more dynamic random access memories (abbreviated as "DRAMs") that are coupled by a memory bus to an interface circuit (implemented by a "north bridge chip") that in turn is coupled to a central processi...

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Bibliographische Detailangaben

Hauptverfasser:	Chen, Andrea Y. J, Yue, Lordson L
Format:	Patent
Sprache:	eng
Online-Zugang:	Volltext bestellen
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