Integrated circuit polysilicon resistor having a silicide extension to achieve 100 % metal shielding from hydrogen intrusion

(1) Field of the Invention A stable, high-value polysilicon resistor is achieved by using a silicide layer that prevents diffusion of hydrogen into the resistor. The resistor can also be integrated into a salicide process for making FETs without increasing process complexity. A polysilicon layer wit...

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Hauptverfasser: Liu, Ruey-Hsin, Tsai, Jun-Lin, Hsu, Yung-Lung
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creator Liu, Ruey-Hsin
Tsai, Jun-Lin
Hsu, Yung-Lung
description (1) Field of the Invention A stable, high-value polysilicon resistor is achieved by using a silicide layer that prevents diffusion of hydrogen into the resistor. The resistor can also be integrated into a salicide process for making FETs without increasing process complexity. A polysilicon layer with a cap oxide is patterned to form FET gate electrodes and the polysilicon resistor. The lightly doped source/drains, insulating sidewall spacers, and source/drain contacts are formed for the FETs. The cap oxide is patterned to expose one end of the resistor, and the cap oxide is removed from the gate electrodes. A refractory metal is deposited and annealed to form the salicide FETs and concurrently to form a silicide on the end of the resistor. The unreacted metal is etched. An interlevel dielectric layer is deposited and contact holes with metal plugs are formed to both ends of the resistor. A metal is deposited to form the first level of metal interconnections, which also provides contacts to both ends of the resistor. The metal is also patterned to form a metal shield over the resistor to prevent hydrogen diffusion into the resistor. In this invention the spacing between the metal portions contacting the ends of the resistor is aligned over the silicide on the resistor to provide 100% shielding from hydrogen diffusion into the resistor.
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The resistor can also be integrated into a salicide process for making FETs without increasing process complexity. A polysilicon layer with a cap oxide is patterned to form FET gate electrodes and the polysilicon resistor. The lightly doped source/drains, insulating sidewall spacers, and source/drain contacts are formed for the FETs. The cap oxide is patterned to expose one end of the resistor, and the cap oxide is removed from the gate electrodes. A refractory metal is deposited and annealed to form the salicide FETs and concurrently to form a silicide on the end of the resistor. The unreacted metal is etched. An interlevel dielectric layer is deposited and contact holes with metal plugs are formed to both ends of the resistor. A metal is deposited to form the first level of metal interconnections, which also provides contacts to both ends of the resistor. The metal is also patterned to form a metal shield over the resistor to prevent hydrogen diffusion into the resistor. In this invention the spacing between the metal portions contacting the ends of the resistor is aligned over the silicide on the resistor to provide 100% shielding from hydrogen diffusion into the resistor.</abstract><oa>free_for_read</oa></addata></record>
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title Integrated circuit polysilicon resistor having a silicide extension to achieve 100 % metal shielding from hydrogen intrusion
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