Method for the planarization of a semiconductor structure
The invention relates to a method for the planarization of a semiconductor structure comprising a substrate, in which several sub-structures (STI; AA; AA′; AA″;) are provided. said sub-structures (STI; AA; AA′; AA″,) having a first sub-structure (AA′) with planar regions (PS) and first trench region...
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| creator | Hollatz, Mark Morhard, Klaus-Dieter Truby, Alexander Tobben, Dirk |
| description | The invention relates to a method for the planarization of a semiconductor structure comprising a substrate, in which several sub-structures (STI; AA; AA′; AA″;) are provided. said sub-structures (STI; AA; AA′; AA″,) having a first sub-structure (AA′) with planar regions (PS) and first trench regions (DT). A layer to be planarized is applied over the semiconductor structure, said layer having appropriate recesses above the first trench regions (DT) of the first sub-structure (AA′). The method comprises the following steps: pre-planarization of the layer to be planarized by an etching step, using a pre-planarization mask, then subsequent planarization of the layer to be planarized by a chemical-mechanical polishing step. According to the invention, a first region (B
1
) is formed on the layer to be planarized above the first sub-structure (AA′) by means of the pre-planarization mask, said region having a predetermined grid of masked and unmasked sections (M
1
; O
1
) are arranged in such a way that they respectively cover both first trench regions (DT) and planar regions (PS), and a supporting structure for the chemical-mechanical polishing step, which corresponds with the masked sections (M
1
) of the grid, is created by the etching step, using the pre-planarization mask. |
| format | Patent |
| fullrecord | <record><control><sourceid>uspatents_EFI</sourceid><recordid>TN_cdi_uspatents_applications_20040127040</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>20040127040</sourcerecordid><originalsourceid>FETCH-uspatents_applications_200401270403</originalsourceid><addsrcrecordid>eNrjZLD0TS3JyE9RSMsvUijJSFUoyEnMSyzKrEosyczPU8hPU0hUKE7NzUzOz0spTS4BKiouKQIySotSeRhY0xJzilN5oTQ3g6aba4izh25pcUFiSWpeSXF8YkFBTmYy2KjieCMDAxMDQyNzIGlMiloA7HI2Aw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method for the planarization of a semiconductor structure</title><source>USPTO Published Applications</source><creator>Hollatz, Mark ; Morhard, Klaus-Dieter ; Truby, Alexander ; Tobben, Dirk</creator><creatorcontrib>Hollatz, Mark ; Morhard, Klaus-Dieter ; Truby, Alexander ; Tobben, Dirk</creatorcontrib><description>The invention relates to a method for the planarization of a semiconductor structure comprising a substrate, in which several sub-structures (STI; AA; AA′; AA″;) are provided. said sub-structures (STI; AA; AA′; AA″,) having a first sub-structure (AA′) with planar regions (PS) and first trench regions (DT). A layer to be planarized is applied over the semiconductor structure, said layer having appropriate recesses above the first trench regions (DT) of the first sub-structure (AA′). The method comprises the following steps: pre-planarization of the layer to be planarized by an etching step, using a pre-planarization mask, then subsequent planarization of the layer to be planarized by a chemical-mechanical polishing step. According to the invention, a first region (B
1
) is formed on the layer to be planarized above the first sub-structure (AA′) by means of the pre-planarization mask, said region having a predetermined grid of masked and unmasked sections (M
1
; O
1
) are arranged in such a way that they respectively cover both first trench regions (DT) and planar regions (PS), and a supporting structure for the chemical-mechanical polishing step, which corresponds with the masked sections (M
1
) of the grid, is created by the etching step, using the pre-planarization mask.</description><language>eng</language><creationdate>2004</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20040127040$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,780,873,885,64057</link.rule.ids><linktorsrc>$$Uhttps://patentcenter.uspto.gov/applications/10692234$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Hollatz, Mark</creatorcontrib><creatorcontrib>Morhard, Klaus-Dieter</creatorcontrib><creatorcontrib>Truby, Alexander</creatorcontrib><creatorcontrib>Tobben, Dirk</creatorcontrib><title>Method for the planarization of a semiconductor structure</title><description>The invention relates to a method for the planarization of a semiconductor structure comprising a substrate, in which several sub-structures (STI; AA; AA′; AA″;) are provided. said sub-structures (STI; AA; AA′; AA″,) having a first sub-structure (AA′) with planar regions (PS) and first trench regions (DT). A layer to be planarized is applied over the semiconductor structure, said layer having appropriate recesses above the first trench regions (DT) of the first sub-structure (AA′). The method comprises the following steps: pre-planarization of the layer to be planarized by an etching step, using a pre-planarization mask, then subsequent planarization of the layer to be planarized by a chemical-mechanical polishing step. According to the invention, a first region (B
1
) is formed on the layer to be planarized above the first sub-structure (AA′) by means of the pre-planarization mask, said region having a predetermined grid of masked and unmasked sections (M
1
; O
1
) are arranged in such a way that they respectively cover both first trench regions (DT) and planar regions (PS), and a supporting structure for the chemical-mechanical polishing step, which corresponds with the masked sections (M
1
) of the grid, is created by the etching step, using the pre-planarization mask.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2004</creationdate><recordtype>patent</recordtype><sourceid>EFI</sourceid><recordid>eNrjZLD0TS3JyE9RSMsvUijJSFUoyEnMSyzKrEosyczPU8hPU0hUKE7NzUzOz0spTS4BKiouKQIySotSeRhY0xJzilN5oTQ3g6aba4izh25pcUFiSWpeSXF8YkFBTmYy2KjieCMDAxMDQyNzIGlMiloA7HI2Aw</recordid><startdate>20040701</startdate><enddate>20040701</enddate><creator>Hollatz, Mark</creator><creator>Morhard, Klaus-Dieter</creator><creator>Truby, Alexander</creator><creator>Tobben, Dirk</creator><scope>EFI</scope></search><sort><creationdate>20040701</creationdate><title>Method for the planarization of a semiconductor structure</title><author>Hollatz, Mark ; Morhard, Klaus-Dieter ; Truby, Alexander ; Tobben, Dirk</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_applications_200401270403</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2004</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Hollatz, Mark</creatorcontrib><creatorcontrib>Morhard, Klaus-Dieter</creatorcontrib><creatorcontrib>Truby, Alexander</creatorcontrib><creatorcontrib>Tobben, Dirk</creatorcontrib><collection>USPTO Published Applications</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Hollatz, Mark</au><au>Morhard, Klaus-Dieter</au><au>Truby, Alexander</au><au>Tobben, Dirk</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method for the planarization of a semiconductor structure</title><date>2004-07-01</date><risdate>2004</risdate><abstract>The invention relates to a method for the planarization of a semiconductor structure comprising a substrate, in which several sub-structures (STI; AA; AA′; AA″;) are provided. said sub-structures (STI; AA; AA′; AA″,) having a first sub-structure (AA′) with planar regions (PS) and first trench regions (DT). A layer to be planarized is applied over the semiconductor structure, said layer having appropriate recesses above the first trench regions (DT) of the first sub-structure (AA′). The method comprises the following steps: pre-planarization of the layer to be planarized by an etching step, using a pre-planarization mask, then subsequent planarization of the layer to be planarized by a chemical-mechanical polishing step. According to the invention, a first region (B
1
) is formed on the layer to be planarized above the first sub-structure (AA′) by means of the pre-planarization mask, said region having a predetermined grid of masked and unmasked sections (M
1
; O
1
) are arranged in such a way that they respectively cover both first trench regions (DT) and planar regions (PS), and a supporting structure for the chemical-mechanical polishing step, which corresponds with the masked sections (M
1
) of the grid, is created by the etching step, using the pre-planarization mask.</abstract><oa>free_for_read</oa></addata></record> |
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| title | Method for the planarization of a semiconductor structure |
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