Semiconductor device and manufacturing method thereof including a probe test step and a burn-in test step

Dispersion of load may be kept within an allowance even when a plurality of probes in a large area are pressed in batch by pressing the probes provided in a membrane to a wafer by applying a pressure load to a plurality of places of a plane of pressure members on the side opposite from the wafer in...

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Hauptverfasser: Kumazawa, Tetsuo, Kohno, Ryuji, Kitano, Makoto, Ariga, Akihiko, Wada, Yuji, Ban, Naoto, Shibuya, Shuji, Motoyama, Yasuhiro, Matsumoto, Kunio, Kasukabe, Susumu, Mori, Terutaka, Shigi, Hidetaka, Watanabe, Takayoshi
Format: Patent
Sprache:eng
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Zusammenfassung:Dispersion of load may be kept within an allowance even when a plurality of probes in a large area are pressed in batch by pressing the probes provided in a membrane to a wafer by applying a pressure load to a plurality of places of a plane of pressure members on the side opposite from the wafer in a probe test step/burn-in test step which is one of semiconductor device manufacturing steps. It is then possible to provide semiconductor devices and a manufacturing method thereof which enhance the reliability and productivity of the semiconductor devices by probing a large number of integrated circuits or a large size integrated circuit in the same time.