Semiconductor chip mounting wafer
A plurality of semiconductor chips such as a dynamic random access memory are formed on a wafer. The semiconductor chips are partitioned by a dicing line region. A silicon oxide film is formed on the wafer. A corrugated groove is formed on an insulating film located in the dicing line region. A meta...
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| creator | Hirokawa, Taichi Kobayashi, Heiji |
| description | A plurality of semiconductor chips such as a dynamic random access memory are formed on a wafer. The semiconductor chips are partitioned by a dicing line region. A silicon oxide film is formed on the wafer. A corrugated groove is formed on an insulating film located in the dicing line region. A metal film such as barrier metal constituting the semiconductor chips is formed so as to cover a surface of the corrugated groove. A film stress of the metal film is dispersed in multiple directions. It is thereby possible to obtain a semiconductor chip mounting wafer capable of ensuring relaxing wafer warping and suppressing an electrostatic chuck error. |
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The semiconductor chips are partitioned by a dicing line region. A silicon oxide film is formed on the wafer. A corrugated groove is formed on an insulating film located in the dicing line region. A metal film such as barrier metal constituting the semiconductor chips is formed so as to cover a surface of the corrugated groove. A film stress of the metal film is dispersed in multiple directions. It is thereby possible to obtain a semiconductor chip mounting wafer capable of ensuring relaxing wafer warping and suppressing an electrostatic chuck error.</abstract><oa>free_for_read</oa></addata></record> |
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| language | eng |
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| source | USPTO Published Applications |
| title | Semiconductor chip mounting wafer |
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