Semiconductor device including a pad and a method of manufacturing the same
A semiconductor device includes a semiconductor substrate including semiconductor elements and an underlie wiring layer, an underlie insulating layer covering the underlie wiring layer; via conductors filled in via holes extending through the underlie insulating layer and reaching the underlie wirin...
Gespeichert in:
Hauptverfasser: | , |
---|---|
Format: | Patent |
Sprache: | eng |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | Yamanoue, Akira Saiki, Takashi |
description | A semiconductor device includes a semiconductor substrate including semiconductor elements and an underlie wiring layer, an underlie insulating layer covering the underlie wiring layer; via conductors filled in via holes extending through the underlie insulating layer and reaching the underlie wiring layer, an insulating stack layer formed on the underlie insulating layer, covering the via conductors, the insulating stack layer including a first and a second insulating layer having different etching characteristic, a pad groove formed through the insulating stack layer, defining a pad region in which the via conductors are exposed, the pad region including therein at least an etching enhancing remaining insulation layer pattern; and a pad conductor filled in the pad groove. |
format | Patent |
fullrecord | <record><control><sourceid>uspatents_EFI</sourceid><recordid>TN_cdi_uspatents_applications_20030057556</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>20030057556</sourcerecordid><originalsourceid>FETCH-uspatents_applications_200300575563</originalsourceid><addsrcrecordid>eNqVyjEKAjEQQNE0FqLeYVoLIbhEDyCKYKn9MiQTdyCZhM3E86vgBSw-v3lLc7tTZl8kdK9lhkAv9gQsPvXA8gSEigFQPkEmnUqAEiGj9Ihe-_w1OhE0zLQ2i4ip0eb3ldlezo_TdddbRSXRNmKtiT0qF2nj3trBWnd07jD8Y98eBzwL</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Semiconductor device including a pad and a method of manufacturing the same</title><source>USPTO Published Applications</source><creator>Yamanoue, Akira ; Saiki, Takashi</creator><creatorcontrib>Yamanoue, Akira ; Saiki, Takashi</creatorcontrib><description>A semiconductor device includes a semiconductor substrate including semiconductor elements and an underlie wiring layer, an underlie insulating layer covering the underlie wiring layer; via conductors filled in via holes extending through the underlie insulating layer and reaching the underlie wiring layer, an insulating stack layer formed on the underlie insulating layer, covering the via conductors, the insulating stack layer including a first and a second insulating layer having different etching characteristic, a pad groove formed through the insulating stack layer, defining a pad region in which the via conductors are exposed, the pad region including therein at least an etching enhancing remaining insulation layer pattern; and a pad conductor filled in the pad groove.</description><language>eng</language><creationdate>2003</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20030057556$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,309,781,874,886,64064</link.rule.ids><linktorsrc>$$Uhttps://patentcenter.uspto.gov/applications/10278939$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Yamanoue, Akira</creatorcontrib><creatorcontrib>Saiki, Takashi</creatorcontrib><title>Semiconductor device including a pad and a method of manufacturing the same</title><description>A semiconductor device includes a semiconductor substrate including semiconductor elements and an underlie wiring layer, an underlie insulating layer covering the underlie wiring layer; via conductors filled in via holes extending through the underlie insulating layer and reaching the underlie wiring layer, an insulating stack layer formed on the underlie insulating layer, covering the via conductors, the insulating stack layer including a first and a second insulating layer having different etching characteristic, a pad groove formed through the insulating stack layer, defining a pad region in which the via conductors are exposed, the pad region including therein at least an etching enhancing remaining insulation layer pattern; and a pad conductor filled in the pad groove.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2003</creationdate><recordtype>patent</recordtype><sourceid>EFI</sourceid><recordid>eNqVyjEKAjEQQNE0FqLeYVoLIbhEDyCKYKn9MiQTdyCZhM3E86vgBSw-v3lLc7tTZl8kdK9lhkAv9gQsPvXA8gSEigFQPkEmnUqAEiGj9Ihe-_w1OhE0zLQ2i4ip0eb3ldlezo_TdddbRSXRNmKtiT0qF2nj3trBWnd07jD8Y98eBzwL</recordid><startdate>20030327</startdate><enddate>20030327</enddate><creator>Yamanoue, Akira</creator><creator>Saiki, Takashi</creator><scope>EFI</scope></search><sort><creationdate>20030327</creationdate><title>Semiconductor device including a pad and a method of manufacturing the same</title><author>Yamanoue, Akira ; Saiki, Takashi</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_applications_200300575563</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2003</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Yamanoue, Akira</creatorcontrib><creatorcontrib>Saiki, Takashi</creatorcontrib><collection>USPTO Published Applications</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Yamanoue, Akira</au><au>Saiki, Takashi</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Semiconductor device including a pad and a method of manufacturing the same</title><date>2003-03-27</date><risdate>2003</risdate><abstract>A semiconductor device includes a semiconductor substrate including semiconductor elements and an underlie wiring layer, an underlie insulating layer covering the underlie wiring layer; via conductors filled in via holes extending through the underlie insulating layer and reaching the underlie wiring layer, an insulating stack layer formed on the underlie insulating layer, covering the via conductors, the insulating stack layer including a first and a second insulating layer having different etching characteristic, a pad groove formed through the insulating stack layer, defining a pad region in which the via conductors are exposed, the pad region including therein at least an etching enhancing remaining insulation layer pattern; and a pad conductor filled in the pad groove.</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | eng |
recordid | cdi_uspatents_applications_20030057556 |
source | USPTO Published Applications |
title | Semiconductor device including a pad and a method of manufacturing the same |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-15T19%3A56%3A24IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-uspatents_EFI&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Yamanoue,%20Akira&rft.date=2003-03-27&rft_id=info:doi/&rft_dat=%3Cuspatents_EFI%3E20030057556%3C/uspatents_EFI%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |