Circuit for selectively generating an output signal from one or more clock signals

The invention relates to a circuit ( 100 ) with which one of a plurality of input clock signals (CLK_SRC 1, . . . , CLK_SCR_n) can be selected and passed on to an output signal (CLK_OUT). The input clock signals are present at a multiplexer (MUX) which applies one of these signals in dependence upon the selection signal (CFG_i) from its control input to its output. The output signal (MUX_OUT) of the multiplexer is applied via a switch (S) and a signal latch (LATCH) to the output of the circuit as output signal (CLK_OUT). Switching between two input signals is controlled by a state machine (FSM) which first intransparently switches the signal latch (LATCH) after a change of the external configuration signal (CFG), then switches the multiplexer (MUX) and transparently switches the signal latch again after the multiplexer output (MUX_OUT) has changed at least once and assumed the value stored in the signal latch. The state machine (FSM) is supplied with its own fast clock (FCLK).