Image processor circuits, systems, and methods

Image processor circuits, systems, and methods

An image processor system for a charge coupled device (CCD) or CMOS imaging system includes a correlated double sample and variable gain (CDSVGA) circuit for receiving data from a CCD system and an automatic gain control (AGC) circuit which first controls gain by adjusting said CCD system and then f...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Chao, Shih-Chung, Johnson, Sandra, Itani, Nadi, Wang, Caiyi, Harris, Brannon, Prabala, Ash, Holberg, Douglas, Hansford, Alan, Azim, Syed, Welland, David
Format: Patent
Sprache:eng
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator Chao, Shih-Chung
Johnson, Sandra
Itani, Nadi
Wang, Caiyi
Harris, Brannon
Prabala, Ash
Holberg, Douglas
Hansford, Alan
Azim, Syed
Welland, David
description An image processor system for a charge coupled device (CCD) or CMOS imaging system includes a correlated double sample and variable gain (CDSVGA) circuit for receiving data from a CCD system and an automatic gain control (AGC) circuit which first controls gain by adjusting said CCD system and then for yet a higher gain level makes gain adjustments in said CDSVGA circuit AND a digital gain circuit to produce a combined target gain level. A processing system for an imager device includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA), an analog-to-digital converter (ADC) coupled to said CDS circuit, a digital gain circuit (DGC) coupled to said ADC, and an automatic gain control (AGC) circuit coupled to said DGC for controlling the CDS circuit and the DGC. The processing circuitry includes an analog front end and a digital signal processing system for capturing full motion video and outputting a CCIR 601 4:2:2 YCrCb video data output for presentation on a user selected display.
format Patent
fullrecord <record><control><sourceid>uspatents_EFI</sourceid><recordid>TN_cdi_uspatents_applications_20020176009</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>20020176009</sourcerecordid><originalsourceid>FETCH-uspatents_applications_200201760093</originalsourceid><addsrcrecordid>eNrjZNDzzE1MT1UoKMpPTi0uzi9SSM4sSi7NLCnWUSiuLC5JzQUyEvNSFHJTSzLyU4p5GFjTEnOKU3mhNDeDpptriLOHbmlxQWJJal5JcXxiQUFOZnJiSWZ-XnG8kYGBkYGhuZmBgaUxKWoBOJ4xew</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Image processor circuits, systems, and methods</title><source>USPTO Published Applications</source><creator>Chao, Shih-Chung ; Johnson, Sandra ; Itani, Nadi ; Wang, Caiyi ; Harris, Brannon ; Prabala, Ash ; Holberg, Douglas ; Hansford, Alan ; Azim, Syed ; Welland, David</creator><creatorcontrib>Chao, Shih-Chung ; Johnson, Sandra ; Itani, Nadi ; Wang, Caiyi ; Harris, Brannon ; Prabala, Ash ; Holberg, Douglas ; Hansford, Alan ; Azim, Syed ; Welland, David</creatorcontrib><description>An image processor system for a charge coupled device (CCD) or CMOS imaging system includes a correlated double sample and variable gain (CDSVGA) circuit for receiving data from a CCD system and an automatic gain control (AGC) circuit which first controls gain by adjusting said CCD system and then for yet a higher gain level makes gain adjustments in said CDSVGA circuit AND a digital gain circuit to produce a combined target gain level. A processing system for an imager device includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA), an analog-to-digital converter (ADC) coupled to said CDS circuit, a digital gain circuit (DGC) coupled to said ADC, and an automatic gain control (AGC) circuit coupled to said DGC for controlling the CDS circuit and the DGC. The processing circuitry includes an analog front end and a digital signal processing system for capturing full motion video and outputting a CCIR 601 4:2:2 YCrCb video data output for presentation on a user selected display.</description><language>eng</language><creationdate>2002</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20020176009$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,776,869,881,64035</link.rule.ids><linktorsrc>$$Uhttps://patentcenter.uspto.gov/applications/10107892$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Chao, Shih-Chung</creatorcontrib><creatorcontrib>Johnson, Sandra</creatorcontrib><creatorcontrib>Itani, Nadi</creatorcontrib><creatorcontrib>Wang, Caiyi</creatorcontrib><creatorcontrib>Harris, Brannon</creatorcontrib><creatorcontrib>Prabala, Ash</creatorcontrib><creatorcontrib>Holberg, Douglas</creatorcontrib><creatorcontrib>Hansford, Alan</creatorcontrib><creatorcontrib>Azim, Syed</creatorcontrib><creatorcontrib>Welland, David</creatorcontrib><title>Image processor circuits, systems, and methods</title><description>An image processor system for a charge coupled device (CCD) or CMOS imaging system includes a correlated double sample and variable gain (CDSVGA) circuit for receiving data from a CCD system and an automatic gain control (AGC) circuit which first controls gain by adjusting said CCD system and then for yet a higher gain level makes gain adjustments in said CDSVGA circuit AND a digital gain circuit to produce a combined target gain level. A processing system for an imager device includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA), an analog-to-digital converter (ADC) coupled to said CDS circuit, a digital gain circuit (DGC) coupled to said ADC, and an automatic gain control (AGC) circuit coupled to said DGC for controlling the CDS circuit and the DGC. The processing circuitry includes an analog front end and a digital signal processing system for capturing full motion video and outputting a CCIR 601 4:2:2 YCrCb video data output for presentation on a user selected display.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2002</creationdate><recordtype>patent</recordtype><sourceid>EFI</sourceid><recordid>eNrjZNDzzE1MT1UoKMpPTi0uzi9SSM4sSi7NLCnWUSiuLC5JzQUyEvNSFHJTSzLyU4p5GFjTEnOKU3mhNDeDpptriLOHbmlxQWJJal5JcXxiQUFOZnJiSWZ-XnG8kYGBkYGhuZmBgaUxKWoBOJ4xew</recordid><startdate>20021128</startdate><enddate>20021128</enddate><creator>Chao, Shih-Chung</creator><creator>Johnson, Sandra</creator><creator>Itani, Nadi</creator><creator>Wang, Caiyi</creator><creator>Harris, Brannon</creator><creator>Prabala, Ash</creator><creator>Holberg, Douglas</creator><creator>Hansford, Alan</creator><creator>Azim, Syed</creator><creator>Welland, David</creator><scope>EFI</scope></search><sort><creationdate>20021128</creationdate><title>Image processor circuits, systems, and methods</title><author>Chao, Shih-Chung ; Johnson, Sandra ; Itani, Nadi ; Wang, Caiyi ; Harris, Brannon ; Prabala, Ash ; Holberg, Douglas ; Hansford, Alan ; Azim, Syed ; Welland, David</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_applications_200201760093</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2002</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Chao, Shih-Chung</creatorcontrib><creatorcontrib>Johnson, Sandra</creatorcontrib><creatorcontrib>Itani, Nadi</creatorcontrib><creatorcontrib>Wang, Caiyi</creatorcontrib><creatorcontrib>Harris, Brannon</creatorcontrib><creatorcontrib>Prabala, Ash</creatorcontrib><creatorcontrib>Holberg, Douglas</creatorcontrib><creatorcontrib>Hansford, Alan</creatorcontrib><creatorcontrib>Azim, Syed</creatorcontrib><creatorcontrib>Welland, David</creatorcontrib><collection>USPTO Published Applications</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Chao, Shih-Chung</au><au>Johnson, Sandra</au><au>Itani, Nadi</au><au>Wang, Caiyi</au><au>Harris, Brannon</au><au>Prabala, Ash</au><au>Holberg, Douglas</au><au>Hansford, Alan</au><au>Azim, Syed</au><au>Welland, David</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Image processor circuits, systems, and methods</title><date>2002-11-28</date><risdate>2002</risdate><abstract>An image processor system for a charge coupled device (CCD) or CMOS imaging system includes a correlated double sample and variable gain (CDSVGA) circuit for receiving data from a CCD system and an automatic gain control (AGC) circuit which first controls gain by adjusting said CCD system and then for yet a higher gain level makes gain adjustments in said CDSVGA circuit AND a digital gain circuit to produce a combined target gain level. A processing system for an imager device includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA), an analog-to-digital converter (ADC) coupled to said CDS circuit, a digital gain circuit (DGC) coupled to said ADC, and an automatic gain control (AGC) circuit coupled to said DGC for controlling the CDS circuit and the DGC. The processing circuitry includes an analog front end and a digital signal processing system for capturing full motion video and outputting a CCIR 601 4:2:2 YCrCb video data output for presentation on a user selected display.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_uspatents_applications_20020176009
source USPTO Published Applications
title Image processor circuits, systems, and methods
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-26T12%3A08%3A42IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-uspatents_EFI&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Chao,%20Shih-Chung&rft.date=2002-11-28&rft_id=info:doi/&rft_dat=%3Cuspatents_EFI%3E20020176009%3C/uspatents_EFI%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true