Vcc independent time delay circuit

Vcc independent time delay circuit

A time delay circuit including a first transistor having a gate, a drain, a source, and a channel between the source and the drain. The input voltage is applied between the gate and drain and the output is taken between the source and drain. The output voltage follows the gate voltage, and the first...

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Hauptverfasser: Wong, Waisum, Rajguru, Chaitanya
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creator Wong, Waisum
Rajguru, Chaitanya
description A time delay circuit including a first transistor having a gate, a drain, a source, and a channel between the source and the drain. The input voltage is applied between the gate and drain and the output is taken between the source and drain. The output voltage follows the gate voltage, and the first transistor gate voltage is substantially constant. The time delay element also includes a delay element, wherein the delay element is coupled to the first trans
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