Semiconductor integrated circuit having functional macro with improved power line connection structure

Semiconductor integrated circuit having functional macro with improved power line connection structure

In a semiconductor integrated circuit having a functional macro, plural first and second power lines extending over the functional macro and supplying first-level and second-level voltages respectively to the functional macro are electrically connected through plural first and second power terminal...

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description In a semiconductor integrated circuit having a functional macro, plural first and second power lines extending over the functional macro and supplying first-level and second-level voltages respectively to the functional macro are electrically connected through plural first and second power terminal patterns to plural third and fourth power lines extending over the semiconductor integrated circuit in the second direction and supplying the first-level and second-level voltages respectively to the semiconductor integrated circuit.
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fullrecord <record><control><sourceid>uspatents_EFI</sourceid><recordid>TN_cdi_uspatents_applications_20010045622</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>20010045622</sourcerecordid><originalsourceid>FETCH-uspatents_applications_200100456223</originalsourceid><addsrcrecordid>eNqVjTEOwjAMRbswIOAOXhmQQoFeAIHYYa-i1G0tpU7kOO31CYgLMP3l_ffWVf_EiVzgLjsNAsSKg1jFDhyJy6Qw2pl4gD6zUwpsPUzWSYCFdASaooS50DEsKOCJEYqN8ctCUineLLitVr31CXe_3VT7--11fRxyiqXGmloboydnP7_U1sYcjTlfmro-_cO-AeNmR_w</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Semiconductor integrated circuit having functional macro with improved power line connection structure</title><source>USPTO Published Applications</source><creator>Iwamoto, Minoru</creator><creatorcontrib>Iwamoto, Minoru</creatorcontrib><description>In a semiconductor integrated circuit having a functional macro, plural first and second power lines extending over the functional macro and supplying first-level and second-level voltages respectively to the functional macro are electrically connected through plural first and second power terminal patterns to plural third and fourth power lines extending over the semiconductor integrated circuit in the second direction and supplying the first-level and second-level voltages respectively to the semiconductor integrated circuit.</description><language>eng</language><creationdate>2001</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20010045622$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,776,869,881,64036</link.rule.ids><linktorsrc>$$Uhttps://patentcenter.uspto.gov/applications/09864445$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Iwamoto, Minoru</creatorcontrib><title>Semiconductor integrated circuit having functional macro with improved power line connection structure</title><description>In a semiconductor integrated circuit having a functional macro, plural first and second power lines extending over the functional macro and supplying first-level and second-level voltages respectively to the functional macro are electrically connected through plural first and second power terminal patterns to plural third and fourth power lines extending over the semiconductor integrated circuit in the second direction and supplying the first-level and second-level voltages respectively to the semiconductor integrated circuit.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2001</creationdate><recordtype>patent</recordtype><sourceid>EFI</sourceid><recordid>eNqVjTEOwjAMRbswIOAOXhmQQoFeAIHYYa-i1G0tpU7kOO31CYgLMP3l_ffWVf_EiVzgLjsNAsSKg1jFDhyJy6Qw2pl4gD6zUwpsPUzWSYCFdASaooS50DEsKOCJEYqN8ctCUineLLitVr31CXe_3VT7--11fRxyiqXGmloboydnP7_U1sYcjTlfmro-_cO-AeNmR_w</recordid><startdate>20011129</startdate><enddate>20011129</enddate><creator>Iwamoto, Minoru</creator><scope>EFI</scope></search><sort><creationdate>20011129</creationdate><title>Semiconductor integrated circuit having functional macro with improved power line connection structure</title><author>Iwamoto, Minoru</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_applications_200100456223</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2001</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Iwamoto, Minoru</creatorcontrib><collection>USPTO Published Applications</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Iwamoto, Minoru</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Semiconductor integrated circuit having functional macro with improved power line connection structure</title><date>2001-11-29</date><risdate>2001</risdate><abstract>In a semiconductor integrated circuit having a functional macro, plural first and second power lines extending over the functional macro and supplying first-level and second-level voltages respectively to the functional macro are electrically connected through plural first and second power terminal patterns to plural third and fourth power lines extending over the semiconductor integrated circuit in the second direction and supplying the first-level and second-level voltages respectively to the semiconductor integrated circuit.</abstract><oa>free_for_read</oa></addata></record>
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title Semiconductor integrated circuit having functional macro with improved power line connection structure
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-22T11%3A19%3A19IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-uspatents_EFI&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Iwamoto,%20Minoru&rft.date=2001-11-29&rft_id=info:doi/&rft_dat=%3Cuspatents_EFI%3E20010045622%3C/uspatents_EFI%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true