Method of manufacturing a transistor
A method of manufacturing a TFT ( 10 ) is disclosed comprising source ( 8 ) and drain ( 8 ″) electrodes joined by a semiconductor channel ( 6 ) formed from a semiconductor layer ( 4 ), a gate insulating layer ( 7 ) and a gate electrode ( 8 ′). The method comprising the steps of applying a foil ( 2 )...
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| creator | Murley, Darren Trainor, Michael |
| description | A method of manufacturing a TFT (
10
) is disclosed comprising source (
8
) and drain (
8
″) electrodes joined by a semiconductor channel (
6
) formed from a semiconductor layer (
4
), a gate insulating layer (
7
) and a gate electrode (
8
′). The method comprising the steps of applying a foil (
2
) comprising a crystallisation enhancing material (CEM) and depositing the semiconductor layer (
4
) over a supporting substrate (
1
); and heating the semiconductor layer (
4
) so as to crystallise the semiconductor layer (
4
) from regions exposed to the CEM of the foil (
2
). The method may further comprise the step of providing a patterned barrier layer (
3
) between the foil (
2
) and the semiconductor layer (
4
) wherein the semiconductor layer (
4
) is crystallised from regions exposed through vias in the barrier layer (
3
) to the CEM of the foil (
2
).
Also disclosed is a TFT (
10
) manufactured by the same, and an active matrix device (
20
) comprising a row and column array of active elements (
22
) wherein each element (
22
) is associated with such a TFT (
10
) connected to corresponding row (
24
) and column (
23
) conductors. |
| format | Patent |
| fullrecord | <record><control><sourceid>uspatents_EFI</sourceid><recordid>TN_cdi_uspatents_applications_20010024866</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>20010024866</sourcerecordid><originalsourceid>FETCH-uspatents_applications_200100248663</originalsourceid><addsrcrecordid>eNrjZFDxTS3JyE9RyE9TyE3MK01LTC4pLcrMS1dIVCgpSswrziwuyS_iYWBNS8wpTuWF0twMmm6uIc4euqXFBYklqXklxfGJBQU5mcmJJZn5ecXxRgYGhgYGRiYWZmbGpKgFACiRLfk</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method of manufacturing a transistor</title><source>USPTO Published Applications</source><creator>Murley, Darren ; Trainor, Michael</creator><creatorcontrib>Murley, Darren ; Trainor, Michael</creatorcontrib><description>A method of manufacturing a TFT (
10
) is disclosed comprising source (
8
) and drain (
8
″) electrodes joined by a semiconductor channel (
6
) formed from a semiconductor layer (
4
), a gate insulating layer (
7
) and a gate electrode (
8
′). The method comprising the steps of applying a foil (
2
) comprising a crystallisation enhancing material (CEM) and depositing the semiconductor layer (
4
) over a supporting substrate (
1
); and heating the semiconductor layer (
4
) so as to crystallise the semiconductor layer (
4
) from regions exposed to the CEM of the foil (
2
). The method may further comprise the step of providing a patterned barrier layer (
3
) between the foil (
2
) and the semiconductor layer (
4
) wherein the semiconductor layer (
4
) is crystallised from regions exposed through vias in the barrier layer (
3
) to the CEM of the foil (
2
).
Also disclosed is a TFT (
10
) manufactured by the same, and an active matrix device (
20
) comprising a row and column array of active elements (
22
) wherein each element (
22
) is associated with such a TFT (
10
) connected to corresponding row (
24
) and column (
23
) conductors.</description><language>eng</language><creationdate>2001</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20010024866$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,777,870,882,64038</link.rule.ids><linktorsrc>$$Uhttps://patentcenter.uspto.gov/applications/09814390$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Murley, Darren</creatorcontrib><creatorcontrib>Trainor, Michael</creatorcontrib><title>Method of manufacturing a transistor</title><description>A method of manufacturing a TFT (
10
) is disclosed comprising source (
8
) and drain (
8
″) electrodes joined by a semiconductor channel (
6
) formed from a semiconductor layer (
4
), a gate insulating layer (
7
) and a gate electrode (
8
′). The method comprising the steps of applying a foil (
2
) comprising a crystallisation enhancing material (CEM) and depositing the semiconductor layer (
4
) over a supporting substrate (
1
); and heating the semiconductor layer (
4
) so as to crystallise the semiconductor layer (
4
) from regions exposed to the CEM of the foil (
2
). The method may further comprise the step of providing a patterned barrier layer (
3
) between the foil (
2
) and the semiconductor layer (
4
) wherein the semiconductor layer (
4
) is crystallised from regions exposed through vias in the barrier layer (
3
) to the CEM of the foil (
2
).
Also disclosed is a TFT (
10
) manufactured by the same, and an active matrix device (
20
) comprising a row and column array of active elements (
22
) wherein each element (
22
) is associated with such a TFT (
10
) connected to corresponding row (
24
) and column (
23
) conductors.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2001</creationdate><recordtype>patent</recordtype><sourceid>EFI</sourceid><recordid>eNrjZFDxTS3JyE9RyE9TyE3MK01LTC4pLcrMS1dIVCgpSswrziwuyS_iYWBNS8wpTuWF0twMmm6uIc4euqXFBYklqXklxfGJBQU5mcmJJZn5ecXxRgYGhgYGRiYWZmbGpKgFACiRLfk</recordid><startdate>20010927</startdate><enddate>20010927</enddate><creator>Murley, Darren</creator><creator>Trainor, Michael</creator><scope>EFI</scope></search><sort><creationdate>20010927</creationdate><title>Method of manufacturing a transistor</title><author>Murley, Darren ; Trainor, Michael</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_applications_200100248663</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2001</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Murley, Darren</creatorcontrib><creatorcontrib>Trainor, Michael</creatorcontrib><collection>USPTO Published Applications</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Murley, Darren</au><au>Trainor, Michael</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method of manufacturing a transistor</title><date>2001-09-27</date><risdate>2001</risdate><abstract>A method of manufacturing a TFT (
10
) is disclosed comprising source (
8
) and drain (
8
″) electrodes joined by a semiconductor channel (
6
) formed from a semiconductor layer (
4
), a gate insulating layer (
7
) and a gate electrode (
8
′). The method comprising the steps of applying a foil (
2
) comprising a crystallisation enhancing material (CEM) and depositing the semiconductor layer (
4
) over a supporting substrate (
1
); and heating the semiconductor layer (
4
) so as to crystallise the semiconductor layer (
4
) from regions exposed to the CEM of the foil (
2
). The method may further comprise the step of providing a patterned barrier layer (
3
) between the foil (
2
) and the semiconductor layer (
4
) wherein the semiconductor layer (
4
) is crystallised from regions exposed through vias in the barrier layer (
3
) to the CEM of the foil (
2
).
Also disclosed is a TFT (
10
) manufactured by the same, and an active matrix device (
20
) comprising a row and column array of active elements (
22
) wherein each element (
22
) is associated with such a TFT (
10
) connected to corresponding row (
24
) and column (
23
) conductors.</abstract><oa>free_for_read</oa></addata></record> |
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| language | eng |
| recordid | cdi_uspatents_applications_20010024866 |
| source | USPTO Published Applications |
| title | Method of manufacturing a transistor |
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